Serial bus protocol encoding for voltage regulator with support for DVFS

1. A control logic for a voltage regulator comprising:

receiving circuitry configured to receive a serial stream comprising a command, wherein the command consists of at most a byte, wherein the command comprises a read/write flag and a voltage change/other flag;

determination circuitry configured to determine a desired output voltage from voltage information in a voltage change information portion of the command when the read flag is set to write and the voltage change/other flag is set to voltage change;

voltage change circuitry configured to change an output voltage of the voltage regulator from a previous output voltage to the new output voltage based on the determined new output voltage, wherein the voltage change circuitry does not change the output voltage of the voltage regulator when the voltage change/other flag is set to other.

2. The control logic of claim 1 further comprising:

chip select circuitry configured to detect when the command is being transmitted to the voltage regulator.

3. The control logic of claim 1 further comprising:

clock receiving circuitry configured to receive a clock signal; and

clock path circuitry configured to use the clock signal to differentiate bits of the command.

4. The control logic of claim 1 wherein the determination circuitry comprises:

circuitry configured to detect a write operation indicator in the command.

5. The control logic of claim 4 wherein the determination circuitry comprises:

circuitry configured to detect a voltage change indicator in the command.

6. The control logic of claim 4 wherein the write operation indicator is a first bit of the command and the voltage change indicator is a second bit in the command.

7. A control system for communicating with a voltage regulator to change an operating voltage of the voltage regulator comprising:

a processor;

memory accessible by the processor that comprises instructions that direct the processor to:

generate a first command having that provides a write instruction, a voltage change instruction, and a desired output voltage instruction wherein a number of bits in the first command is less than or equal to a byte,

transmit the first command to a voltage regulator,

generate a second command that provides a write instruction, an other function instruction, and a series of bits encoding the other function, wherein a number of bits in the second command is equal to the number of bits in the first command, and

transmit the second command to the voltage regulator.

8. The control system of claim 7 wherein the instructions further include instructions that direct the processor to:

generate a select signal that indicates the voltage regulator is to receive the first and second command, and

apply the select signal to a select path connected to the voltage regulator.

9. The control system of claim 7 wherein the instructions further include instructions that direct the processor:

obtain a clock signal; and

provide the clock signal to the voltage regulator over a clock path.

10. The control system of claim 7 wherein the instructions to generate the first command include instructions that direct the processor to:

insert the write operation instruction in the first command.

11. The control system of claim 10 wherein the instructions to generate the first command include instructions that direct the processor to:

insert the voltage change instruction in the first command.

12. The control system of claim 10 wherein the write operation command is a first bit of the first command and the voltage change command is a second bit in the first command.

13. The control system of claim 7 wherein the instructions further direct the processor to:

generate the desired output voltage instruction; and

encode the desired output voltage instruction into the first command wherein the desired output voltage instruction is three to six bits in length.

14. The control logic of claim 1 , wherein the receiving circuitry is configured to receive the serial stream from an SPI (serial data protocol) interface via an SPI protocol.

15. The control logic of claim 14 , wherein the serial stream comprises an SPI command having a length of 3 bytes.

16. The control logic of claim 1 , wherein the determination circuitry comprises a selector that receives at least three bits of the command to select the desired output voltage from at least one of eight voltage levels stored in a register of a register bank.

17. The control logic of claim 15 , wherein a voltage reference generator comprises the determination circuitry.