Serial bus auto-addressing
A bus node is capable of performing a method, for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes of the data bus system in an assignment time period. After the assigning of bus node addresses to the bus nodes in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.
1. A method for controlling a serial data bus system comprising:
a bus line;
a bus master connected to the bus line; and
a plurality of bus nodes serially connected to the bus line; wherein the plurality of bus nodes includes:
at least two addressable bus nodes configured to receive addresses in an addressing phase; and
zero or more standard bus nodes having respectively already fixed addresses;
wherein the method includes the addressing phase for assigning addresses to at least one of the at least two addressable bus nodes, and an operating phase for operating the serial data bus system after termination of the addressing phase;
wherein, in the addressing phase, at least two of the plurality of bus nodes are operative to feed into the bus line a respective current flowing to the bus master, and the plurality of bus nodes includes:
a first bus node, connected to the bus line at a site upstream from, and closest to the bus master;
a last bus node, connected to the bus line at a site upstream from, and farthest from the bus master; and
zero or more middle bus nodes, connected to the bus line in between the first bus node and the last bus node;
wherein:
each of the at least two addressable bus nodes is configured to receive a respective address assigned from the bus master during the addressing phase and comprises a respective current measurement circuit adapted to be switched into the bus line and a respective controllable bypass switch connected in parallel to the respective current measurement circuit, and,
each of the zero or more standard bus nodes has the respective address that is fixed prior to performing the addressing phase,
wherein, in the method;
in the addressing phase, the respective address is assigned to the at least one of the at least two addressable bus nodes in an open state of the respective controllable bypass switch, and
in the operating phase, the respective current measurement circuit of the at least one addressed addressable bus node is bypassed by closing the respective controllable bypass switch.
2. The method according to claim 1 , wherein the addressing phase comprises a plurality of addressing cycles, and, for each of the addressing cycles:
an address is assigned respectively to one of the addressable bus nodes that has not yet been assigned an address; and
the one of the addressable bus nodes, after the address is assigned, will, for a remainder of the addressing phase, not participate in further address assigning for other not-yet-addressed addressable bus nodes, and further wherein, for the one of the addressable bus nodes, after the address is assigned, the current measurement circuit is bypassed by closing the bypass switch connected in parallel to the current measurement circuit.
3. The method according to claim 1 , wherein, in the addressing phase, each addressable bus node that has not yet been assigned an address during the addressing phase is operative to feed into the bus line a respective address current flowing to the bus master, the respective address current flowing through the current measurement circuit of the respective addressable bus node that has not yet been assigned an address.
4. The method according to claim 2 , wherein, in the addressing phase, each addressable bus node that has not yet been assigned an address during the addressing phase is operative to feed into the bus line a respective address current flowing to the bus master, the respective address current flowing through the current measurement circuit of the respective addressable bus node that has not yet been assigned an address.
5. The method according to claim 1 , wherein the current measurement circuit includes a shunt resistor.
6. The method according to claim 2 , wherein the current measurement circuit includes a shunt resistor.
7. The method according to claim 3 , wherein the current measurement circuit includes a shunt resistor.
8. The method according to claim 4 , wherein the current measurement circuit includes a shunt resistor.
9. An addressable bus node for a serial data bus system, the serial data bus system comprising:
a bus line;
a bus master connected to the bus line; and
a plurality of bus nodes serially connected to the bus line; wherein the plurality of bus nodes includes:
at least two addressable bus nodes configured to receive addresses assigned by the bus master in an addressing phase; and
zero or more standard bus nodes having respectively an already fixed address: each of the at least two addressable bus nodes comprising:
a respective current measurement circuit adapted to be switched into the bus line;
a respective bypass switch connected in parallel to the current measurement circuit;
a respective addressing current source for feeding into the bus line an address current flowing into the bus master; and
a respective control unit for controlling the respective bypass switch;
wherein, in an addressing phase of the serial data bus system for assignment of an address, the respective control unit is programmed to control the respective bypass switch to assume an open state, and, in an operative phase of the serial data bus system occurring after termination of the addressing phase, the respective control unit is operative to control the respective bypass switch to assume a closed state.
10. The addressable bus node according to claim 9 , wherein the respective current measurement circuit is operative to capture the address current fed from the respective addressing current source into the bus line.