Three-dimensional memory device with corrosion-resistant composite spacer
Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of conductor/dielectric layer pairs, a plurality of memory strings each extending vertically through the memory stack, a slit contact disposed laterally between the plurality of memory strings, and a composite spacer disposed laterally between the slit contact and at least one of the memory strings. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film disposed laterally between the first silicon oxide film and the second silicon oxide film.
1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of conductor/dielectric layer pairs;
a plurality of memory strings each extending vertically through the memory stack;
a slit contact disposed laterally between the plurality of memory strings; and
a composite spacer disposed laterally between the slit contact and at least one of the memory strings,
wherein the composite spacer comprises a high dielectric constant (high-k) dielectric film comprising aluminum oxide, a first silicon oxide film disposed laterally between the slit contact and the high-k dielectric film and formed by a process performed not lower than about 400° C., and a second silicon oxide film disposed laterally between the high-k dielectric film and the at least one of the memory strings and formed by a process performed not higher than about 400° C., wherein the high-k dielectric film comprises a plurality of dielectric sub-films stacked laterally and extending across the plurality of conductor/dielectric layer pairs, and the first silicon oxide film is present in a recessed area of a gate structure formed by a recessed gate conductor, while the second silicon oxide film and the high-k dielectric film are not present in the recessed area of the gate structure.
2. The 3D memory device of claim 1 , wherein a thickness of the high-k dielectric film is between about 1 nm and about 10 nm.
3. The 3D memory device of claim 2 , wherein the thickness of the high-k dielectric film is between about 3 nm and about 7 nm.
4. The 3D memory device of claim 1 , wherein the plurality of dielectric sub-films comprise a plurality of dielectric materials.
5. The 3D memory device of claim 1 , wherein each of the conductor/dielectric layer pairs comprises a conductor layer comprising tungsten.
6. The 3D memory device of claim 1 , wherein the slit contact comprises tungsten.
7. The 3D memory device of claim 1 , wherein each of the memory strings comprises:
a semiconductor channel extending vertically through the conductor/dielectric layer pairs; and
a memory film disposed laterally between the conductor/dielectric layer pairs and the semiconductor channel.
8. The 3D memory device of claim 1 , wherein each of the slit contact and the composite spacer is in a nominally stripe shape in a plan view.
9. The 3D memory device of claim 1 , wherein the slit contact is electrically connected to sources of at least two of the memory strings.
10. A semiconductor device, comprising:
a memory stack comprising a plurality of conductor/dielectric layer pairs;
a contact extending vertically through the memory stack; and
a composite spacer disposed laterally between the contact and conductor layers of the memory stack,
wherein the composite spacer comprises a first silicon oxide film formed by a process performed not higher than about 600° C., a second silicon oxide film formed by a process performed not lower than about 600° C., and a high dielectric constant (high-k) dielectric film comprising aluminum oxide disposed laterally between the first silicon oxide film and the second silicon oxide film, wherein the first silicon oxide film is present in a recessed area of a gate structure formed by a recessed gate conductor, while the second silicon oxide film and the high-k dielectric film are not present in the recessed area of the gate structure.
11. A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of conductor/dielectric layer pairs;
a plurality of memory strings each extending vertically through the memory stack;
a slit contact disposed laterally between the plurality of memory strings; and
a composite spacer disposed laterally between the slit contact and at least one of the memory strings,
wherein the composite spacer comprises a high dielectric constant (high-k) dielectric film comprising aluminum oxide, a first silicon oxide film disposed laterally between the slit contact and the high-k dielectric film and formed by a process performed not lower than about 600° C., and a second silicon oxide film disposed laterally between the high-k dielectric film and the at least one of the memory strings and formed by a process performed not higher than about 400° C., wherein the high-k dielectric film comprises a plurality of dielectric sub-films stacked laterally and extending across the plurality of conductor/dielectric layer pairs, and the first silicon oxide film is present in a recessed area of a gate structure formed by a recessed gate conductor, while the second silicon oxide film and the high-k dielectric film are not present in the recessed area of the gate structure.
12. The 3D memory device of claim 11 , wherein a thickness of the high-k dielectric film is between about 1 nm and about 10 nm.
13. The 3D memory device of claim 12 , wherein the thickness of the high-k dielectric film is between about 3 nm and about 7 nm.
14. The 3D memory device of claim 11 , wherein the plurality of dielectric sub-films comprise a plurality of dielectric materials.
15. The 3D memory device of claim 11 , wherein each of the conductor/dielectric layer pairs comprises a conductor layer comprising tungsten.
16. The 3D memory device of claim 11 , wherein the slit contact comprises tungsten.
17. The 3D memory device of claim 11 , wherein each of the memory strings comprises:
a semiconductor channel extending vertically through the conductor/dielectric layer pairs; and
a memory film disposed laterally between the conductor/dielectric layer pairs and the semiconductor channel.
18. The 3D memory device of claim 11 , wherein the slit contact is electrically connected to sources of at least two of the memory strings.