Apparatus for adjusting delay of command signal path
An example apparatus includes a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal, a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal, a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal, and a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.
1. An apparatus comprising:
a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal;
a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal;
a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a delay amount between the first clock signal and the second clock signal being a first time;
a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a delay amount between the first clock signal and the third clock signal being a second time that is shorter than the first time;
a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal; and
a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.
2. The apparatus of claim 1 , wherein the first circuit is configured to activate the first enable signal over a plurality of cycles of the first clock signal so that the first latch circuit receives a plurality of active edges of the second clock signal in response to the first command signal.
3. The apparatus of claim 2 , wherein the second circuit is configured to activate the second enable signal over a plurality of cycles of the first clock signal so that the second latch circuit receives a plurality of active edges of the third clock signal in response to the second command signal.
4. The apparatus of claim 1 , wherein the first command signal comprises a chip select signal.
5. The apparatus of claim 1 , wherein the second command signal comprises at least one of a read command and a write command.
6. The apparatus of claim 1 , further comprising:
a first delay line through which the first clock signal passes; and
a second delay line through which the fourth command signal passes.
7. The apparatus of claim 6 , wherein the second delay line has substantially a same delay amount as the first delay line.
8. The apparatus of claim 1 , further comprising a clock input buffer circuit configured to generate the first clock signal based on an external clock signal.
9. The apparatus of claim 8 , further comprising a command decoder circuit configured to generate the second command signal by decoding an external command signal synchronized with the external clock signal.
10. The apparatus of claim 1 , wherein the third circuit includes a delay element delaying the first clock signal to generate the second clock signal.
11. An apparatus comprising:
a clock input buffer circuit configured to generate a first clock signal based on an external clock signal;
a command decoder circuit configured to generate a first command signal by decoding an external command signal synchronized with the external clock signal;
a first clock control circuit configured to generate a second clock signal that is delayed from the first clock signal in a first delay amount;
a second clock control circuit configured to generate a third clock signal that is delayed from the first clock signal in a second delay amount;
a first latch circuit configured to latch the first command signal in response to the second clock signal to generate a second command signal; and
a second latch circuit configured to latch the second command signal in response to the third clock signal to generate a third command signal,
wherein the first clock control circuits stops generating the second clock signal when a first enable signal is deactivated, and
wherein the second clock control circuit stops generating the third clock signal when a second enable signal different from the first enable signal is deactivated.
12. The apparatus of claim 11 , wherein the first delay amount s greater than the second delay amount.
13. The apparatus of claim 12 , wherein the first enable signal is activated before the second enable signal is activated.
14. The apparatus of claim 13 , wherein the first enable signal is deactivated before the second enable signal is deactivated.
15. The apparatus of claim 14 , wherein both the first and second enable signals are in an active state during a predetermined period.
16. The apparatus of claim 11 , further comprising:
a first delay line through which the first clock signal passes; and
a second delay line through which the third command signal passes.
17. The apparatus of claim 16 , wherein the second delay line has substantially a same delay amount as the first delay line.
18. An apparatus comprising:
a first delay line configured to receive a first clock signal;
a first latch circuit configured to latch a first command signal in response to a second clock signal to generate a second command signal;
a second latch circuit configured to latch the second command signal in response to a third clock signal to generate a third command signal;
a second delay line configured to receive the third command signal;
a first clock control circuit configured to generate the second clock signal; and
a second clock control circuit configured to generate the third clock signal,
wherein the first clock control circuit is activated before the second clock control circuit is activated, and
wherein the first clock control circuit is deactivated before the second clock control circuit is deactivated.
19. The apparatus of claim 18 , wherein a phase difference between the first and second clock signals is greater than a phase difference between the first and third clock signals.
20. The apparatus of claim 18 , wherein the second delay line has substantially a same delay amount as the first delay line.
21. An apparatus comprising:
a clock control circuit configured to receive a first clock signal and output a second clock signal responsive to an enable signal;
a latch circuit configured to latch a command signal responsive to the second clock signal;
a circuit configured to produce the enable signal responsive to a chip select signal and the first clock signal;
an additional latch circuit configured to latch a command signal output from the latch circuit responsive to a third clock signal;
an additional clock control circuit configured to receive the first clock signal and output the third clock signal responsive to a second enable signal; and
an additional circuit configured to produce the second enable signal responsive to the command signal and the first clock signal.