System level interconnect with programmable switching
View Patent ↗In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.
1. An apparatus comprising:
a first configurable digital processing block; and
a programmable digital interconnect coupled to the first configurable digital processing block, the programmable digital interconnect operable to couple the first configurable digital processing block to:
a plurality of input/output (I/O) ports,
at least one peripheral unit, and
at least one processing element operable to send or receive control signals from the configurable digital processing block.
2. The apparatus of claim 1 , further comprising a second configurable digital processing block coupled to the programmable digital interconnect, wherein the second configurable digital processing block and the first configurable digital processing block are operable together to execute complex digital operations.
3. The apparatus of claim 1 , wherein the at least one peripheral unit is a fixed function peripheral.
4. The apparatus of claim 1 , wherein the at least one peripheral unit is a configurable peripheral.
5. The apparatus of claim 1 , wherein the at least one peripheral unit comprises a first fixed function peripheral and a second configurable peripheral.
6. The apparatus of claim 1 , wherein the control signals correspond to at least one event generated by the at least one processing element.
7. The apparatus of claim 6 , wherein the control signal is an interrupt provided by the at least one processing element.
8. The apparatus of claim 1 , wherein the first configurable digital processing block is disposed on the same silicon substrate as the at least one processing element.
9. The apparatus of claim 1 , wherein the first configurable digital processing block is disposed on the same silicon substrate as the at least one peripheral unit.
10. The apparatus of claim 1 , wherein the at least one processing element is operable to provide connectivity between a first peripheral and a second peripheral of the at least one peripheral, and wherein the configurable digital processing block is operable to route signals between the first peripheral and the second peripheral.
11. A system comprising:
an array of configurable digital processing blocks; and
a programmable digital interconnect coupled to the array of configurable digital processing blocks, the programmable digital interconnect operable to couple the at least one configurable digital processing block of the array of configurable digital processing blocks to:
a plurality of input/output (I/O) ports,
at least one peripheral unit, and
at least one processing element operable to send or receive control signals from the at least one configurable digital processing block of the array of configurable digital processing blocks.
12. The system of claim 11 , wherein a first and second configurable digital block of the array of configurable digital blocks are operable together to execute complex digital operations.
13. The system of claim 11 , wherein the at least one peripheral unit is a fixed function peripheral.
14. The system of claim 11 , wherein the at least one peripheral unit is a configurable peripheral.
15. The system of claim 11 , wherein the at least one peripheral unit comprises a first fixed function peripheral and a second configurable peripheral.
16. The system of claim 11 , wherein the control signals correspond to at least one event generated by the at least one processing element.
17. The system of claim 16 , wherein the control signal is an interrupt provided by the at least one processing element.
18. The system of claim 11 , wherein the array of configurable digital processing blocks is disposed on the same silicon substrate as the at least one processing element.
19. The system of claim 11 , wherein the array of configurable digital processing blocks is disposed on the same silicon substrate as the at least one peripheral unit.
20. The system of claim 11 , wherein the at least one processing element is operable to provide connectivity between a first peripheral and a second peripheral of the at least one peripheral, and wherein the array of configurable digital processing blocks is operable to route signals between the first peripheral and the second peripheral.