IP Library Granted Patent US 10,716,231
Granted Patent B2
US 10,716,231 · App. 16/146,908 · Granted Jul 14, 2020

Pin count socket having reduced pin count and pattern transformation

Inventors: Srikant Nekkanty (Chandler, AZ); Zhichao Zhang (Chandler, AZ); Kemal Aygun (Tempe, AZ)
Assignee: Intel Corporation
H05K7/1084H05K1/0296H05K1/115H05K7/1459H05K2201/10325H05K2201/10371H05K2201/10378
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Quick Facts
Patent No.
US 10,716,231
App. No.
16/146,908
Granted
Jul 14, 2020
Kind
B2
Abstract

An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

Claims (75)

1. An electronic package adapter comprising:

an interposer comprising a first plurality of contacts on a first surface and a second plurality of contacts on a second surface opposing the first surface, the first and second plurality of contacts extend parallel with the first and second surfaces,

wherein the first plurality of contacts is in electrical contact with the second plurality of contacts,

the first plurality of contacts has a configuration pattern for electrical contact with an electronic package,

the second plurality of contacts has a configuration pattern for electrical contact with a motherboard, and

the first and second plurality of contacts have different numbers of contacts.

2. The electronic package adapter of claim 1 , wherein:

the first and second plurality of contacts comprise ground and signal contacts, and

the first plurality of contacts has a higher ratio of signal contacts to ground contacts than the second plurality of contacts.

3. The electronic package adapter of claim 2 , wherein:

the number of the second plurality of contacts is larger than that of the first plurality of contacts.

4. The electronic package adapter of claim 1 , wherein:

the first and second plurality of contacts have different arrangements of ground and signal contacts.

5. The electronic package adapter of claim 4 , wherein:

the first plurality of contacts has a plurality of first cells, each first cell having the signal contacts of the first cell surrounded by the ground contacts of the first cell.

6. The electronic package adapter of claim 5 , wherein:

the second plurality of contacts has a plurality of second cells, each second cell having a pattern in which the signal contacts of the second cell are surrounded by the ground contacts of the second cell, and

the ground contacts of the second cell are fewer than the ground contacts of the first cell.

7. The electronic package adapter of claim 6 , wherein:

the number of signal contacts of each first and second cell are equal.

8. The electronic package adapter of claim 1 , wherein the interposer further comprises:

ground shielding vias between signal connections that connect signal contacts of the first and second plurality of contacts, each signal connection isolated by the ground shielding vias, and

a ground plane to which the ground shielding vias are connected.

9. The electronic package adapter of claim 8 , wherein:

at least some of the signal connections extend vertically straight through the interposer and at least some of the signal connections are bent.

10. The electronic package adapter of claim 1 , further comprising:

a shielded socket having signal socket housings for signal pins of the package and ground socket housings for ground pins of the package,

wherein the shielded socket comprises ground shielding vias between the signal socket housings, and

the ground socket housings comprise plated socket housings to short the ground pins.

11. The electronic package adapter of claim 10 , wherein:

spatial and arrangement transformation of signals and ground from the package to the motherboard occurs in the interposer and does not occur in the shielded socket.

12. The electronic package adapter of claim 1 , wherein:

the first plurality of contacts has smaller pin-to-pin pitch than the second plurality of contacts.

13. An interposer comprising:

a first set of contacts on a first surface;

a second set of contacts on a second surface opposing the first surface, the first and second set of contacts extend parallel with the first and second surfaces; and

an insulator disposed between the first and second surfaces, the insulator comprising vias through which the first and second set of contacts are electrically connected,

wherein the first and second set of contacts comprises signal and ground contacts and have different ratios of signal to ground contacts.

14. The interposer of claim 13 , wherein:

the first set of contacts has a configuration pattern for electrical contact with an electronic package,

the second set of contacts has a configuration pattern for electrical contact with a motherboard, and

the first set of contacts has a higher ratio of signal contacts to ground contacts than the second set of contacts.

15. The interposer of claim 14 , wherein:

the first set of contacts has first cells, each first cell having the signal contacts of the first cell surrounded by the ground contacts of the first cell,

the second set of contacts second cells, each second cell having a pattern in which the signal contacts of the second cell are surrounded by the ground contacts of the second cell,

the ground contacts of the second cell are fewer than the ground contacts of the first cell, and

the number of signal contacts of each first and second cell are equal.

16. The interposer of claim 14 , wherein the insulator further comprises:

ground shielding vias between the vias connecting signal contacts of the first and second set of contacts.

17. The interposer of claim 16 , wherein:

each signal via is electrically isolated from other signal vias by the ground shielding vias, and

the insulator further comprises a ground plane to which the ground shielding vias are connected.

18. An electronic system comprising:

an electronic package containing package circuitry and signal and ground pins extending from the package and configured to provide signals and ground, respectively, to the package circuitry;

a motherboard containing motherboard circuitry and motherboard signal and ground contacts configured to provide signals and ground, respectively, between the motherboard circuitry and the package circuitry; and

an interposer between the package and the motherboard, the interposer comprising:

a first set of signal and ground contacts on a first surface opposing the package;

a second set of signal and ground contacts on a second surface opposing the motherboard the first and second set of signal and ground contacts extend parallel with the first and second surfaces; and

an insulator disposed between the first and second surfaces, the insulator comprising vias through which the first and second set of signal contacts are electrically connected and the first and second set of ground contacts are electrically connected,

wherein the first set of signal and ground contacts has a higher ratio of signal to ground contacts than the second set of signal and ground contacts.

19. The electronic system of claim 18 , wherein the insulator further comprises:

ground shielding vias between the vias connecting signal contacts of the first and second set of contacts, each signal via electrically isolated from other signal vias by the ground shielding vias, and

a ground plane to which the ground shielding vias are connected.

20. The electronic system of claim 18 , further comprising:

a shielded socket on which the package is mounted, the shielded socket having signal socket mountings for the signal pins of the package and ground socket mountings for the ground pins of the package,

wherein the shielded socket comprises ground shielding vias between the signal socket mountings, and

the ground socket mountings comprise plated socket housings.

21. The electronic package adapter of claim 1 , wherein:

the interposer further comprises an insulator through which the first and second plurality of contacts are connected,

adjacent contacts of the first plurality of contacts are isolated in laterally perpendicular directions by the insulator, the laterally perpendicular directions parallel with the first and second surfaces, and

adjacent contacts of the second plurality of contacts are isolated in the laterally perpendicular directions by the insulator.

22. The electronic package adapter of claim 1 , wherein:

the interposer is substantially rectangular,

an entirety of the first plurality of contacts is substantially collinear with a portion of the first surface between the first plurality of contacts, and

an entirety of the second plurality of contacts is substantially collinear with a portion of the second surface between the second plurality of contacts.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2019
From: NEKKANTY, SRIKANT; ZHANG, ZHICHAO; AYGUN, KEMAL
To: INTEL CORPORATION
Reel/Frame 049115/0447 →
Continuity (1)
Related Publication 20200107463A1 · Apr 2, 2020