Anti-eclipse circuitry with tracking of floating diffusion reset level
View Patent ↗Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.
1. An imager, comprising:
a pixel array including a plurality of imaging pixels, a first non-imaging pixel configured to produce a first nominal reset signal, and a second non-imaging pixel configured to produce a second nominal reset signal having a different signal level than the first nominal reset signal;
control circuitry operably coupled to the pixel array and configured to—
output image signals based on reset signals produced by corresponding ones of the imaging pixels,
adjust a signal level of a reset signal of one of the imaging pixels proximate the first-non-imaging pixel based at least in part on the first nominal reset signal, and
adjust a signal level of a reset signal of another one of the imaging pixels proximate the second-non-imaging pixel based at least in part on the second nominal reset signal.
2. The imager of claim 1 , further comprising:
a first sample-and-hold circuit configured to sample and hold a voltage signal corresponding to the first nominal reset signal; and
a second sample-and-hold circuit configured to sample and hold a voltage signal corresponding to the second nominal reset signal.
3. The imager of claim 1 , further comprising:
a first anti-eclipse circuit coupled to the first non-imaging pixel and one of the imaging pixels; and
a second anti-eclipse circuit coupled to the second non-imaging pixel and another one of the imaging pixels.
4. The imager of claim 1 wherein the first and second non-imaging pixels are shielded from incident light.
5. The imager of claim 1 wherein the first and second nominal reset signals have different signal levels due to variances in semiconductor fabrication.
6. An imager, comprising:
a pixel array including an imaging pixel having a first floating diffusion node, and a dark pixel having a second floating diffusion node; and
control circuitry operably coupled to the first and second floating diffusion nodes and configured to produce an output signal based at least in part on—
charge stored at the first floating diffusion node, and
charge stored at the second floating diffusion node during an eclipse condition at the first floating diffusion node.
7. The imager of claim 6 , further comprising:
a first sample-and-hold circuit configured to store a voltage based on the charge stored at the first floating diffusion node; and
a second sample-and-hold circuit configured to store a voltage based on the charge stored at the second floating diffusion node.
8. The imager of claim 6 wherein the control circuitry is configured to produce a voltage signal based on an offset voltage and the charge stored at the second floating diffusion node during the eclipse condition.
9. The imager of claim 6 , further comprising:
a first anti-eclipse circuit coupled to one of the imaging pixels and the first non-imaging pixel; and
a second anti-eclipse circuit coupled to another one of the imaging pixels and the second non-imaging pixel.
10. The imager of claim 6 wherein the imaging and non-imaging pixels are configured to be switchably controlled by the same switch signal.
11. The imager of claim 6 wherein the dark pixel includes a light sensitive element that is shielded from incident light.