Semiconductor integrated circuit device including nano-wire selector and method of manufacturing the same

1. A method of manufacturing a semiconductor integrated circuit device, the method comprising:

forming an active region including a nano-wire on a bulk insulating layer;

forming a work function-controlling region in the active region;

forming a gate insulating layer on the nano-wire;

forming a first conductive layer having a first work function on the bulk insulating layer;

etching the first conductive layer to form a first gate configured to surround one portion of the nano-wire;

forming a second conductive layer having a second work function on a surface of the nano-wire with the first gate; and

etching the second conductive layer to form second gates at both sides of the first gate,

wherein the second work function is lower than the first work function, and

wherein the work function-controlling region is formed to overlap at least one of the second gates at the both sides of the first gate.

2. The method of claim 1 , wherein the work function-controlling region is formed to overlap at least one of the second gates.

3. The method of claim 1 , wherein etching the first conductive layer comprises anisotropically etching the first conductive layer, and

wherein etching the second conductive layer comprises anisotropically etching the second conductive layer.

4. A semiconductor integrated circuit device comprising:

a semiconductor substrate including a bulk insulating layer

an active region formed over the bulk insulating layer, the active region including a nano-wire being parallel with a surface of the semiconductor substrate and pad regions connected with both sides of the nano-wire, wherein the nano-wire is spaced apart from a surface of the bulk insulating layer by a depth;

a gate formed to surround one portion of the nano-wire;

a source formed in the active region corresponding to an one side of the gate;

a drain formed in the active region corresponding to the other side of the gate; and

a work function-controlling region formed in the nano-wire to overlap at least one of the both sides of the gate to have a shape of a junction region,

wherein the work function-controlling region includes a semiconductor material having a band gap different from a band gap of the nano-wire, and

wherein the gate comprises:

a first gate surrounding a central portion of the nano-wire, the first gate having a first work function; and

second gates formed at sidewalls of the first gate, the second gates having a second work function lower than the first work function,

wherein the second gates are adjacent to the source and drain.

5. The semiconductor integrated circuit device of claim 4 , wherein the work function-controlling region is formed to face bottom surfaces of the second gates, respectively.

6. The semiconductor integrated circuit device of claim 4 , wherein the work function-controlling region is formed to face a bottom surface of the second gate adjacent to the drain region.

7. A semiconductor integrated circuit device comprising:

a bulk insulating layer having a groove;

an active region formed over the bulk insulating layer, the active region including a nano-wire and pad regions connected with both sides of the nano-wire, wherein the nano-wire is formed on the groove and the pad regions are formed on the bulk insulating layer;

a gate including a first gate formed to surround one portion of the nano-wire and a second gates formed at sidewalls of the first gate, wherein a work function of the second gate is lower than that of the first gate;

junction regions formed in the active region on both sides of the gate; and

a work function-controlling region formed in the nano-wire to overlap the second gates,

wherein the work function-controlling region includes a semiconductor material having a band gap different from a band gap of the nano-wire.

8. The semiconductor integrated circuit device of claim 7 , wherein the junction regions include a source formed in the nano wire and one of the pad regions where correspond to an one side of the gate, and a drain formed in the nano wire and the other one of the pad regions where correspond to the other side of the gate.