Method for estimating data retention time in a solid state drive
A system for controlling a solid state drive is disclosed that includes a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks. A pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices. An effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device.
1. A system for controlling a solid state drive, comprising:
a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks;
a pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices; and
an effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device.
2. The system of claim 1 further comprising a read trim analysis system configured to determine an optimal read trim for a NAND memory device.
3. The system of claim 2 further comprising an error correction code system configured to determine an error correction code value for one or more of the pages of each of the NAND memory devices, and wherein the read trim analysis system is configured to receive the error correction code value and to determine the optimal read trim using the error correction code value.
4. The system of claim 1 wherein the effective retention time system is configured to determine a retention time for each page of a plurality of pages of a selected block.
5. The system of claim 1 wherein the effective retention time system is configured to determine a retention time for each page of a plurality of pages of a selected block and to statistically combine the retention time for each page of the selected block to obtain an effective retention time for the selected block.
6. The system of claim 1 wherein the pseudo clock system is further configured to determine a pseudo clock value for each block of a plurality of blocks of a selected NAND memory device.
7. The system of claim 1 wherein the pseudo clock system is further configured to determine a pseudo clock value for each block of a plurality of blocks of a selected NAND memory device and to statistically combine the pseudo clock values to obtain a NAND memory device pseudo clock value.
8. A method for controlling a solid state drive, comprising:
selecting a number of blocks of a NAND memory device for data retention time estimation;
using a predetermined set of read trims to generate a plurality of retention times for each of the blocks; and
generating a pseudo clock value based on the read trims that result in a lowest retention time for each of the blocks.
9. The method of claim 8 wherein using the predetermined set of read trims to generate the plurality of retention times for each of the blocks comprises using the predetermined set of read trims to generate a plurality of retention times for each of a plurality of pages for one or more of the blocks.
10. The method of claim 8 further comprising statistically combining the plurality of retention times for each of the blocks.
11. A system for controlling a solid state drive, comprising:
a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks:
a pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices;
an effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device;
a read trim analysis system configured to determine an optimal read trim for a NAND memory device; and
wherein the effective retention time system is configured to determine a retention time for each page of a plurality of pages of a selected block.
12. The system of claim 11 further comprising an error correction code system configured to determine an error correction code value for one or more of the pages of each of the NAND memory devices, and wherein the read trim analysis system is configured to receive the error correction code value and to determine the optimal read trim using the error correction code value.
13. The system of claim 11 wherein the effective retention time system is configured to determine a retention time for each page of a plurality of pages of a selected block and to statistically combine the retention time for each page of the selected block to obtain an effective retention time for the selected block.
14. The system of claim 11 wherein the pseudo clock system is further configured to determine a pseudo clock value for each block of a plurality of blocks of a selected NAND memory device.
15. The system of claim 11 wherein the pseudo clock system is further configured to determine a pseudo clock value for each block of a plurality of blocks of a selected NAND memory device and to statistically combine the pseudo clock values to obtain a NAND memory device pseudo clock value.
16. The system of claim 1 further comprising a read trim analysis system igured to determine an optimal read trim for a NAND memory device, wherein the effective retention time system is configured to determine a retention time for each page of a plurality of pages of a selected block and to statistically combine the retention time for each page of the selected block to obtain an effective retention time for the selected block.
17. The system of claim 1 further comprising a read trim analysis system configured to determine an optimal read trim for a NAND memory device, wherein the pseudo clock system is further configured to determine a pseudo clock value for each block of a plurality of blocks of a selected NAND memory device.
18. The system of claim 1 further comprising a read trim analysis system configured to determine an optimal read trim for a NAND memory device, wherein the pseudo clock system is further configured to determine a pseudo clock value for each block of a plurality of blocks of a selected NAND memory device and to statistically combine the pseudo clock values to obtain a NAND memory device pseudo clock value.
19. The system of claim 1 further comprising:
a read trim analysis system configured to determine an optimal read trim for a NAND memory device;
an error correction code system configured to determine an error correction code value for one or more of the pages of each of the NAND memory devices, and wherein the read trim analysis system is configured to receive the error correction code value and to determine the optimal read trim using the error correction code value and the effective retention time system is configured to determine a retention time for each page of a plurality of pages of a selected block.
20. The system of claim 1 further comprising:
a read trim analysis system configured to determine an optimal read trim for a NAND memory device;
an error correction code system configured to determine an error correction code value for one or more of the pages of each of the NAND memory devices, and wherein the read trim analysis system is configured to receive the error correction code value and to determine the optimal read trim using the error correction code value and the effective retention time system is configured to determine a retention time for each page of a plurality of pages of a selected block and to statistically combine the retention time for each page of the selected block to obtain an effective retention time for the selected block.