IP Library Granted Patent US 10,374,612
Granted Patent B1
US 10,374,612 · App. 16/151,902 · Granted Aug 6, 2019

Ancilla qubit devices in a superconducting quantum processor

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Quick Facts
Patent No.
US 10,374,612
App. No.
16/151,902
Granted
Aug 6, 2019
Kind
B1
Abstract

In a general aspect, a quantum computing system includes ancilla qubit devices. In some aspects, a quantum computing system includes a quantum processor cell that includes a superconducting quantum circuit system. The superconducting quantum circuit system includes a tunable-frequency primary qubit device; a flux-bias device coupled to the tunable-frequency primary qubit device; and a fixed-frequency ancilla qubit device. The fixed-frequency ancilla qubit device is connected only to the tunable-frequency primary qubit device in the superconducting quantum circuit system. The quantum computing system also includes a control system communicably coupled to the quantum processor cell. The control system is configured to apply a parametrically-activated two-qubit quantum logic gate to the tunable-frequency primary qubit device and the fixed-frequency ancilla qubit device by sending, to the flux-bias device, a radio-frequency control signal that modulates the tunable-frequency primary qubit device.

Claims (50)

1. A quantum computing system comprising:

a quantum processor cell comprising a superconducting quantum circuit system, the superconducting quantum circuit system comprising:

a tunable-frequency primary qubit device;

a flux-bias device coupled to the tunable-frequency primary qubit device; and

a fixed-frequency ancilla qubit device connected only to the tunable-frequency primary qubit device; and

a control system communicably coupled to the quantum processor cell and configured to apply a parametrically-activated two-qubit quantum logic gate to the tunable-frequency primary qubit device and the fixed-frequency ancilla qubit device, wherein the control system is configured to apply the parametrically-activated two-qubit quantum logic gate by sending, to the flux-bias device, a radio-frequency control signal that modulates the tunable-frequency primary qubit device.

2. The quantum computing system of claim 1 , wherein the superconducting quantum circuit system comprises a capacitive connection that connects the tunable-frequency primary qubit device and the fixed-frequency ancilla qubit device.

3. The quantum computing system of claim 1 , wherein the superconducting quantum circuit system comprises a readout resonator device connected to the tunable-frequency primary qubit device.

4. The quantum computing system of claim 3 , wherein the control system is configured to detect a quantum state of the tunable-frequency primary qubit device by sending a control signal to the tunable-frequency primary qubit device through the readout resonator device.

5. The quantum computing system of claim 3 , wherein the superconducting quantum circuit system comprises at least one other qubit device connected to the tunable-frequency primary qubit device.

6. The quantum computing system of claim 5 , wherein the at least one other qubit device includes at least one other ancilla qubit device.

7. The quantum computing system of claim 6 , wherein the at least one other qubit device includes at least one other primary qubit device.

8. The quantum computing system of claim 1 , wherein the parametrically-activated two-qubit quantum logic gate comprises an iSWAP gate.

9. The quantum computing system of claim 1 , wherein the parametrically-activated two-qubit quantum logic gate comprises a controlled-Z gate.

10. The quantum computing system of claim 1 , wherein the control system is configured to operate the fixed-frequency ancilla qubit device as a memory qubit device without a dedicated readout device connected to the fixed-frequency ancilla qubit device.

11. The quantum computing system of claim 1 , wherein the control system is configured to operate the fixed-frequency ancilla qubit device in the application of an error correcting code.

12. The quantum computing system of claim 1 , wherein the quantum processor cell comprises a number of primary qubit devices, and the control system is configured to use the fixed-frequency ancilla qubit device to extend a quantum computational capacity of the quantum processor cell beyond the number of primary qubit devices in the quantum processor cell.

13. The quantum computing system of claim 1 , wherein the control system is configured to:

obtain a binary readout value by measuring a first qubit device in the quantum processor cell; and

store the binary readout value in the fixed-frequency ancilla qubit device.

14. A quantum computing method comprising:

storing information in a quantum processor cell comprising a superconducting quantum circuit system, the superconducting quantum circuit system comprising:

a tunable-frequency primary qubit device;

a flux-bias device coupled to the tunable-frequency primary qubit device; and

a fixed-frequency ancilla qubit device connected only to the tunable-frequency primary qubit device; and

by operation of a control system communicably coupled to the quantum processor cell, applying a parametrically-activated two-qubit quantum logic gate to the tunable-frequency primary qubit device and the fixed-frequency ancilla qubit device, wherein applying the parametrically-activated two-qubit quantum logic gate comprises sending, to the flux-bias device, a radio-frequency control signal that modulates the tunable-frequency primary qubit device.

15. The quantum computing method of claim 14 , wherein the superconducting quantum circuit system comprises a readout resonator device connected to the tunable-frequency primary qubit device, and the method comprises detecting a quantum state of the tunable-frequency primary qubit device by sending a control signal to the tunable-frequency primary qubit device through the readout resonator device.

16. The quantum computing method of claim 14 , wherein applying the parametrically-activated two-qubit quantum logic gate comprises applying an iSWAP gate.

17. The quantum computing method of claim 14 , wherein applying the parametrically-activated two-qubit quantum logic gate comprises applying a controlled-Z gate.

18. The quantum computing method of claim 14 , comprising operating the ancilla qubit device as a memory qubit device without a dedicated readout device connected to the ancilla qubit device.

19. The quantum computing method of claim 14 , comprising operating the fixed-frequency ancilla qubit device in an error correcting code.

20. The quantum computing method of claim 14 , wherein the quantum processor cell comprises a number of primary qubit devices, and the method comprises using the fixed-frequency ancilla qubit device to extend a quantum computational capacity of the quantum processor cell beyond the number of primary qubit devices in the quantum processor cell.

21. The quantum computing method of claim 14 , comprising:

obtaining a binary readout value by measuring a first qubit device in the quantum processor cell; and

storing the binary readout value in the fixed-frequency ancilla qubit device.

22. The quantum computing method of claim 21 , further comprising retrieving the binary readout value from the fixed-frequency ancilla qubit device.

23. A quantum computing system comprising:

a quantum processor cell comprising a superconducting quantum circuit system, the superconducting quantum circuit system comprising:

tunable-frequency primary qubit devices;

flux-bias devices coupled to the respective tunable-frequency primary qubit devices;

fixed-frequency ancilla qubit devices, each fixed-frequency ancilla qubit device connected only to a respective one of the tunable-frequency primary qubit devices; and

connections between neighboring pairs of primary and ancilla qubit devices, each neighboring pair comprising one of the tunable-frequency primary qubit devices and one of the fixed-frequency ancilla qubit devices; and

a control system communicably coupled to the quantum processor cell and configured to apply parametrically-activated two-qubit quantum logic gates to the neighboring pairs, wherein the control system is configured to apply the parametrically-activated two-qubit quantum logic gates by sending, to the flux-bias device coupled to the tunable-frequency primary qubit device in a respective neighboring pair, a radio-frequency control signal that modulates the tunable-frequency primary qubit device in the respective neighboring pair.

24. The quantum computing system of claim 23 , comprising additional connections between neighboring pairs of primary qubit devices, each neighboring pair of primary qubit devices comprising at least one of the tunable-frequency primary qubit devices.

25. The quantum computing system of claim 23 , wherein the superconducting quantum circuit system comprises readout resonator devices connected to the respective tunable-frequency primary qubit devices.

26. The quantum computing system of claim 23 , wherein each of the tunable-frequency primary qubit devices is connected to exactly one of the fixed-frequency ancilla qubit devices.

27. The quantum computing system of claim 23 , wherein each of the tunable-frequency primary qubit devices is connected to more than one of the fixed-frequency ancilla qubit devices.

28. The quantum computing system of claim 23 , wherein the control system is configured to operate the fixed-frequency ancilla qubit devices as memory qubit devices without dedicated readout devices connected to the ancilla qubit devices.

29. The quantum computing system of claim 23 , wherein the control system is configured to operate the fixed-frequency ancilla qubit devices in an error correcting code.

30. The quantum computing system of claim 23 , wherein the quantum processor cell comprises a number of primary qubit devices, and the control system is configured to use the fixed-frequency ancilla qubit devices to extend a quantum computational capacity of the quantum processor cell beyond the number of primary qubit devices in the quantum processor cell.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC
Reel/Frame 069603/0771 →
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
Reel/Frame 069603/0831 →
AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Jul 8, 2024
From: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
To: TRINITY CAPITAL INC.
Reel/Frame 068146/0416 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Mar 10, 2021
From: RIGETTI & CO, INC.
To: TRINITY CAPITAL INC.
Reel/Frame 055557/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2019
From: SINCLAIR, RODNEY FRANKLYN; REAGOR, MATTHEW J.
To: RIGETTI & CO, INC.
Reel/Frame 048643/0988 →
Cited By (7)
US 12,402,543 US 12,407,340 US 12,555,015 US 12,555,017 US 12,632,761 US 12,676,616 US 12,694,319