High-speed phase interpolator

1. A phase interpolator device comprising:

a clock buffer for receiving input clock signals and providing buffered clock signals, the input clock signals including a first clock signal and a second clock signal, the first clock signal and the second clock signal being separated by a predetermined phase, the buffered clock signals including a first buffered clock signal and a second buffered clock signal,

a digital-analog-converter (DAC) module comprising DAC blocks and being configured to generate an intermediate clock signal, the DAC blocks including a first DAC block and a second DAC block, the first DAC block being configured to process the first buffered clock signal and contribute to the intermediate clock signal at a first time interval at a first predetermined weight, the second DAC block being configured to process the second buffered clock signal and contribute to the intermediate clock signal at a second time interval at a second predetermined weight, the first time interval partially overlapping the second time interval; and

a clock generator configured to generate an output clock signal using at least the intermediate clock signal;

wherein the first DAC block is configured to operate in a mixing mode until a predetermined trip point is reached.

2. The device of claim 1 wherein:

the buffered clock signals further comprising a third buffered clock signal and a fourth buffered clock signal;

the DAC module further comprising a third DAC block and a fourth DAC block, the third DAC block being configured to process the third buffered clock signal and contribute to the intermediate clock signal at a third time interval at a third predetermined weight.

3. The device of claim 1 first comprising a bias generator configured to generate a control signal, the control signal being associated with a duration of the first time interval.

4. The device of claim 1 wherein the two or fewer buffered clock signals are active at the same time.

5. The device of claim 1 wherein the first weight is stored as a 6-bit value.

6. The device of claim 1 wherein the first DAC block further comprises a capacitor to integrate current from the bias signal when operating in the mixing mode.

7. The device of claim 1 wherein the first DAC block is coupled to a supply voltage, the first DAC block being configured to ramp from the supply voltage until the trip point is reached.

8. The device of claim 7 wherein the supply voltage is a positive supply voltage (VDDA) or a negative supply voltage (VSSA).

9. The device of claim 7 wherein the first DAC block is characterized by a ramp rate based on the first weight.

10. The device of claim 1 wherein the output clock signal is characterized by a 50% duty cycle.

11. The device of claim 1 wherein the first buffered clock signal and the second buffered clock signal are separated by a 90 degrees phase shift.

12. The device of claim 1 wherein the bias signal is associated with a clock period of the input clock signal.

13. The device of claim 1 wherein the first DAC block uses the control signal from the bias generator as a unit current.

14. A communication system comprising

a phase interpolator device that comprises:

an interface for receiving four clock signals, the four clock signals including a first clock signal and a second clock signal, the first clock signal and the second clock signal being separated by a 90-degree phase; and

a digital-analog-converter (DAC) module comprising DAC blocks and being configured to generate an intermediate clock signal, the DAC blocks including a first DAC block and a second DAC block, the first DAC block being configured to process the first clock signal and contribute to the intermediate clock signal at a first time interval at a first predetermined weight, the second DAC block being configured to process the second clock signal and contribute to the intermediate clock signal at a second time interval at a second predetermined weight, the first time interval partially overlapping the second time interval;

wherein:

the first DAC block is configured to operate in a mixing mode until a predetermined trip point is reached;

the first DAC block comprises a reset block for generating a reset signal to stop the mixing mode.

15. The system of claim 14 wherein the reset block generates the reset signal based at least on the intermediate clock signal.

16. A method for generating fractional phase signals, the method comprising:

receiving four clock signals, the four clock signals including a first clock signal and a second clock signal, the first clock signal and the second clock signal being separated by a 90-degree phase;

generating a control signal, the control signal being associated with a clock period of the four clock signals;

assigning a first weight value to the first clock signal;

assigning a second weight value to the second clock signal;

accumulating an intermediate signal using a unit current based on the first weight value and the first clock signal during a first time interval during a mixing mode;

accumulating the intermediate signal using the unit current based on the second weight value and the second clock signal during a second time interval during a mixing mode;

generating a reset signal to terminate the mixing mode; and

generating an output clock signal based on the intermediate signal.

17. The method of claim 16 further comprising:

receiving a first digital value associated with the first weight value;

converting the first digital value to the first weight value using a DAC.

18. The method of claim 16 wherein the first time interval is initiated by a rising edge of first clock signal and terminated by a mixing mode trip point.

19. The method of claim 16 further comprising generating the unit current through a feedback loop.

20. The method of claim 16 wherein the first time interval and the second time interval partially overlap.