Systems and methods for generating clock signals
The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.
1. A clock generator device comprising:
a source clock configured to generate a reference clock signal;
a clock multiplier configured to generate a multiplied clock signal on a feedback path by multiplying the reference clock signal by a factor;
a jitter measurement circuit coupled to the clock multiplier and configured to generate a compensation signal on a second path by sampling jitter of the reference clock signal associated with the multiplied clock signal based on a jitter reference signal providing a stable reference for jitter reduction, the jitter measurement circuit being configured to operate at a lowered frequency, the lowered frequency being lower than a frequency of the multiplied clock signal, wherein the jitter measurement circuit comprises a coarse jitter measurement path and a fine measurement jitter path, the coarse and fine jitter measurements from the coarse and fine jitter measurement paths being summed for a total litter value indicative of jitter associated with the reference clock signal; and
an adjustment circuit coupled to the clock multiplier and the jitter measurement circuit, the adjustment circuit being configured to generate a corrected signal based on the multiplied clock signal, the compensation signal, and the total jitter value.
2. The clock generator device of claim 1 further comprising an output circuit for processing the corrected signal and generating an output clock signal compensated for jitter.
3. The clock generator device of claim 1 wherein the jitter reference signal comprises a statistical signal providing the stable reference for jitter reduction.
4. The clock generator device of claim 1 wherein the jitter reference signal comprises a delay signal providing the stable reference for jitter reduction.
5. The clock generator device of claim 1 wherein the jitter reference signal comprises a reference voltage providing the stable reference for jitter reduction.
6. The clock generator device of claim 1 wherein the adjustment circuit comprises a first phase interpolator for rotating phase interpolation.
7. The clock generator device of claim 6 wherein the adjustment circuit comprises a second phase interpolator for static phase interpolation, the second phase interpolator matching the first phase interpolator.
8. A clock generator device comprising:
a source clock configured to generate a reference clock signal;
a clock multiplier configured to generate a multiplied clock signal on a feedback path by multiplying the reference clock signal by a factor; and
an adjustment circuit coupled to the clock multiplier and a jitter measurement circuit, the adjustment circuit configured to generate a corrected signal based on the multiplied clock signal, a compensation signal, and a total jitter value indicative of jitter associated with the reference clock signal;
wherein the jitter measurement circuit comprises a lookup table on a second path for jitter adjustment and is configured to generate the compensation signal by sampling jitter of the reference clock signal associated with the multiplied clock signal based on a jitter reference signal providing a stable reference for jitter reduction, the jitter measurement circuit being configured to operate at a lowered frequency, the lowered frequency being lower than a frequency of the multiplied clock signal, and
wherein the jitter measurement circuit further comprises a coarse jitter measurement path and a fine measurement jitter path on the second path, the coarse and fine jitter measurements from the coarse and fine litter measurement paths being summed for the total jitter value.
9. The clock generator device of claim 8 further comprising an output circuit for processing the corrected signal and generating an output clock signal compensated for jitter.
10. The clock generator device of claim 8 wherein the jitter reference signal comprises a statistical signal, a delay signal, or a reference voltage providing the stable reference for jitter reduction.
11. The clock generator device of claim 8 wherein the adjustment circuit comprises a first phase interpolator for rotating phase interpolation.
12. The clock generator device of claim 11 wherein the adjustment circuit comprises a second phase interpolator for static phase interpolation, the second phase interpolator matching the first phase interpolator.
13. A clock generator device comprising:
a source clock configured to generate a reference clock signal;
a clock multiplier configured to generate a multiplier clock signal on a feedback path by multiplying the reference clock signal by a factor, the clock multiplier being configured to remove phase noise in the reference clock signal;
a jitter measurement circuit coupled to the clock multiplier and configured to generate a compensation signal on a second path by sampling jitter of the reference clock signal associated with the multiplied clock signal based on a jitter reference signal providing a stable reference for jitter reduction, the measurement circuit being configured to operate at a lowered frequency relative to a frequency of the multiplied clock signal, the jitter measurement circuit comprising a high-pass filter for removing jitter and comprising a coarse jitter measurement path and a fine fitter measurement path, the coarse and fine jitter measurements from the coarse and fine jitter measurement paths being summed for a total jitter value indicative of jitter associated with the reference clock signal; and
an adjustment circuit coupled to the clock multiplier and the jitter measurement circuit, the adjustment circuit being configured to generate a corrected signal based on the multiplied clock signal, the compensation signal, and the total jitter value.
14. The clock generator device of claim 13 wherein the adjustment circuit comprises a first phase interpolator for rotating phase interpolation.
15. The clock generator device of claim 14 wherein the adjustment circuit comprises a second phase interpolator for static phase interpolation, the second phase interpolator matching the first phase interpolator.
16. The clock generator device of claim 13 further comprising an output circuit for processing the corrected signal and generating an output clock signal compensated for jitter.
17. The clock generator device of claim 13 wherein the jitter reference signal comprises a statistical signal, a delay signal, or a reference voltage providing the stable reference for jitter reduction.