Device for verifying data transmissions and method using the same
View Patent ↗A device using parity for verification of data transmitted from a first device through a data line to a second device includes a processor and a memory. The data line includes first to fourth pins for transmitting data and fifth to eighth pins for transmitting parity information. The processor receives values of first to eighth pins, calculates sum of the values of combinations of the first to fourth pins for data and applies modular operations on results of the four combinations. Equality or non-equality with the parity values of the fifth to eighth pins is determined, and the second device is permitted to receive the data when the results correspond, the modular operation being a (mod 2) operation. A method applied to such device is also disclosed.
1. A data transmission parity method for verifying data transmitted from a first device through a data line to a second device, the data line comprising a first to a fourth signal pins for transmitting data, the data line further comprising a fifth to an eighth signal pins for transmitting parity information, the method comprising:
receiving and acquiring signal values of the first to the eighth signal pins, and defining each three signal pins of the first to the fourth signal pins as a first to a fourth pin combination;
calculating a sum of the signal values of each of the first to the fourth pin combination, and respectively executing a modular operation on each of the sum to obtain a first to a fourth results;
determining whether the first to the fourth results are correspondingly equal to the signal values of the fifth to the eighth signal pins; and
controlling the second device to receive the data when the first to the fourth results are correspondingly equal to the signal values of the fifth to the eighth signal pins.
2. The data transmission parity method of claim 1 , further comprising:
controlling the second device to reject the data when at least one of the first to the fourth results is not correspondingly equal to one of the signal values of the fifth to the eighth signal pins.
3. The data transmission parity method of claim 1 , further comprising:
determining failed pins in the first to the fourth signal pins when at least one of the first to the fourth results is not correspondingly equal to one of the signal values of the fifth to the eighth signal pins; and
repairing the failed pins and controlling the second device to receive the data.
4. The data transmission parity method of claim 1 , wherein the data line is a CAT5 cable.
5. A data transmission parity device for verifying data transmitted from a first device through a data line to a second device, the data line comprising a first to a fourth signal pins for transmitting data, the data line further comprising a fifth to an eighth signal pins for transmitting parity information, the data transmission parity device comprising:
a processor; and
a memory storing a plurality of instructions, which when executed by the processor, cause the processor to:
receive and obtain signal values of the first to the eighth signal pins, and define each three signal pins of the first to the fourth signal pins as a first to a fourth pin combination;
calculate a sum of the signal values of the first to the fourth pin combination and respectively apply a modular operation on each of the sum to obtain a first to a fourth results;
determine whether the first to the fourth results are correspondingly equal to the signal values of the fifth to the eighth signal pins; and
control the second device to receive the data when the first to the fourth results are correspondingly equal to the signal values of the fifth to the eighth signal pins.
6. The data transmission parity device of claim 5 , further comprising:
controlling the second device to reject the data when at least one of the first to the fourth results is not correspondingly equal to one of the signal values of the fifth to the eighth signal pins.
7. The data transmission parity device of claim 5 , further comprising:
determining failed pins in the first to the fourth signal pins when at least one of the first to the fourth results is not correspondingly equal to one of the signal values of the fifth to the eighth signal pins; and
repairing the failed pins and controlling the second device to receive the data.
8. The data transmission parity device of claim 5 , wherein the data line is a CAT5 cable.
9. A data transmission parity device for verifying data transmitted from a first device through a data line to a second device, the data line comprising a first to a fourth signal pins for transmitting data, the data line further comprising a fifth to an eighth signal pins for transmitting parity information, the data transmission parity device comprising:
a processor; and
a memory storing a plurality of instructions, which when executed by the processor, cause the processor to:
receive and obtain signal values of the first to the eighth signal pins, and define each three signal pins of the first to the fourth signal pins as a first to a fourth pin combination;
calculate a sum of the signal values of the first to the fourth pin combination and respectively apply a modular operation on each of the sum to obtain a first to a fourth results;
determine whether the first to the fourth results are correspondingly equal to the signal values of the fifth to the eighth signal pins;
control the second device to receive the data when the first to the fourth results are correspondingly equal to the signal values of the fifth to the eighth signal pins;
determine failed pins in the first to the fourth signal pins when at least one of the first to the fourth results is not correspondingly equal to one of the signal values of the fifth to the eighth signal pins; and
repair the failed pins and control the second device to receive the data.
10. The data transmission parity device of claim 9 , wherein the data line is a CAT5 cable.