Three-dimensional memory device and manufacturing method thereof

1. A three-dimensional memory device comprising:

a plurality of bottom source lines extending in a first horizontal direction;

a stacked structure disposed on the bottom source lines, wherein the stacked structure includes a plurality of composite structures which are spaced apart from one another and respectively located at different levels, each of the composite structures includes a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer;

a plurality of bit lines disposed on the stacked structure and extending in a second horizontal direction, wherein the bit lines traverse the bottom source lines; and

a plurality of pillar structures passing through the stacked structure, wherein each of the pillar structures is connected between the corresponding bit line and the corresponding bottom source line, and each of the composite structures and the corresponding one of the pillar structures define a memory cell;

wherein each of the pillar structures includes a barrier layer, a gate insulating layer, and a channel layer, and each of the ferroelectric layers and the corresponding one of the gate insulating layers are insulated from each other by the corresponding one of the barrier layers.

2. The three-dimensional memory device according to claim 1 , wherein the barrier layer is an outermost layer in each of the pillar structures, each of the pillar structures further includes a core insulation column, and the channel layer is interposed between the core insulation column and the gate insulating layer.

3. The three-dimensional memory device according to claim 1 , wherein the barrier layer is made of a conductive material and insulated from both of the corresponding bit line and the corresponding bottom source line.

4. The three-dimensional memory device according to claim 3 , wherein each of the channel layers has two ends respectively connected to the corresponding bottom source line and the corresponding bit line.

5. The three-dimensional memory device according to claim 1 , wherein the stacked structure includes a plurality of insulating layers, and each of the composite structures is disposed in a space defined by two adjacent insulating layers.

6. The three-dimensional memory device according to claim 5 , wherein the ferroelectric layer of each of the composite structures conformingly covers a part of a sidewall surface of the corresponding one of the pillar structures, an upper surface of one of the adjacent insulating layers, and a lower surface of the other one of the adjacent insulating layers.

7. The three-dimensional memory device according to claim 1 , further comprising a dielectric layer disposed on the top of the stacked structure, being in contact with the bit lines, and having a plurality of openings respectively corresponding to the pillar structures, wherein each of the bit lines has a plurality of conductive portions respectively filled in the openings to be electrically connected to the corresponding the pillar structures.

8. The three-dimensional memory device according to claim 1 , wherein the ferroelectric layer is made of a material including a ferroelectric material and dopants, the ferroelectric material is hafnium oxide, hafnium zirconium oxide, hafnium silicon oxide or zirconium titanium oxide, and the dopants are silicon, aluminum, lanthanum, yttrium, strontium, gadolinium, niobium, nickel, tantalum, or any combination thereof.

9. The three-dimensional memory device according to claim 1 , wherein the stacked structure has a cell region, the pillar structures are arranged in the cell region;

wherein the three-dimensional memory device includes two isolation portions respectively located at two opposite sides of the cell region, and each of the isolation portions extends from a top surface of the stacked structure to a bottom surface of the stacked structure.