Frequency hopping pattern for unlicensed internet-of-things system

1. An apparatus for generating a frequency hopping sequence in an unlicensed Internet-of-Things (IoT) system, the apparatus comprising: a baseband circuitry that includes:

one or more processors to generate a frequency hopping sequence by conducting a permutation operation based on a physical cell identifier (PCI) and a system frame number (SFN), and to select a channel within an unlicensed spectrum according to the frequency hopping sequence; and

a memory interface to receive data identifying at least one of the PCI or the SFN,

wherein the one or more processors are to:

conduct two separate permutation operations to generate two sequences, respectively; and

conduct a logical combination of the two sequences to generate the frequency hopping sequence.

2. The apparatus as claimed in claim 1 , wherein, for each of the two separate permutation operations, the one or more processors are further to obtain one of a most significant bit, a least significant bit, an odd bit and an even bit of the SFN as a first parameter, to generate a second parameter based on a function of the PCI and the SFN, and to conduct the permutation operation using the first parameter and the second parameter respectively as input and control of the permutation operation.

3. The apparatus as claimed in claim 2 , wherein the one or more processors are to generate the second parameter based on:

Y =PCI×32+SFN′; and

SFN′=floor[(SFN+eFrame×1024)/8],

where Y is the second parameter, eFrame is the least significant 3 bits of a hyperframe index, and floor denotes a flooring function.

4. The apparatus as claimed in claim 3 , wherein the one or more processors are to generate the frequency hopping sequence Φ(xi) with xi expressed by:

xi ={Perm5(SFN′ 10,8,6,4,2, Y )XOR Perm5(NOT SFN′ 9,7,5,3,1, NOT Y )} mod|Φ|+1,

where |Φ| denotes dimension of the frequency hopping sequence, and the notation of X N1,N2,N3,N4,N5 denotes the N1 th , N2 th , N3 th , N4 th and N5 th least significant bits of parameter X in binary form.

5. The apparatus as claimed in claim 1 , wherein, for each of the two separate permutation operations, the one or more processors are further to obtain one of a most significant bit, a least significant bit, an odd bit and an even bit of the SFN as a first parameter, to generate a second parameter based on a pseudorandom number generator using the PCI as a seed, and to conduct the permutation operation using the first parameter and the second parameter respectively as input and control of the permutation operation.

6. The apparatus as claimed in claim 5 , wherein the one or more processors are to generate the second parameter based on Y=1−[Ψ], where Y is the second parameter, Ψ denotes initial 14 values generated by the pseudorandom number generator with the seed equal to the PCI, and [Ψ] indicates an operation of rounding Ψ.

7. The apparatus as claimed in claim 6 , wherein the one or more processors are to generate the frequency hopping sequence Φ(xi) with xi expressed by:

xi ={Perm5(SFN′ 10,8,6,4,2, Y )XOR Perm5(NOT SFN′ 9,7,5,3,1, NOT Y )} mod|Φ|+1; and

SFN′=floor[(SFN+eFrame×1024)/8],

where eFrame is the least significant 3 bits of a hyperframe index, the notation of X N1,N2,N3,N4,N5 denotes the N1 th , N2 th , N3 th , N4 th and N5 th least significant bits of parameter X in binary form, and floor denotes a flooring function.

8. An apparatus for generating a frequency hopping sequence in an unlicensed Internet-of-Things (IoT) system, the apparatus comprising: a baseband circuitry that includes:

one or more processors to generate a frequency hopping sequence by conducting a permutation operation based on a physical cell identifier (PCI) and a system frame number (SFN), and to select a channel within an unlicensed spectrum according to the frequency hopping sequence; and

a memory interface to receive data identifying at least one of the PCI or the SFN,

wherein the one or more processors are to generate the frequency hopping sequence Φ(xi) with xi=Perm5(z, P)+1, where parameter z is a combination of the PCI and the SFN, and parameter P is a function of the PCI, the SFN and a total number of frequency channels.

9. The apparatus as claimed in claim 8 , wherein the one or more processors are to calculate the parameter z based on one of the following equations:

z ={SFN′ 1,2,3,4,5 +PCI 1,2,3,4,5 +PCI 5,6,7,8,9 } mod N ; and

z ={SFN′ 1,2,3,4,5 +PCI 1,2,3,4,5 XOR SFN′ 6,7,8,9,10 } mod N,

where SFN′=floor[(SFN+eFrame×1024)/8], N is the total number of frequency channels, eFrame is the least significant 3 bits of a hyperframe index, the notation of X N1,N2,N3,N4,N5 denotes the N1 th , N2 th , N3 th , N4 th and N5 th least significant bits of parameter X in binary form, and floor denotes a flooring function.

10. The apparatus as claimed in claim 9 , wherein the one or more processors are to calculate the parameter P based on:

P=P ′ if N= 32;

P=P ′ with P 11,9,8,5,4 =[0,0,0,0,0] if N= 16; and

P ′={PCI+SFN′ 6,7,8,9,10 +512×SFN′ 6,7,8,9,10 +N× ( N− 16)/16+SFN′ 5 ×(32 −N )×32} mod 2 14 .

11. The apparatus as claimed in claim 9 , wherein the one or more processors are to calculate the parameter P based on:

P=P ′ if N= 32;

P=P ′ with P 11,9,8,5,4 =[0,0,0,0,0] if N= 16; and

P ′=PCI+512×SFN′ 6,7,8,9,10 .

12. The apparatus as claimed in claim 8 , wherein the one or more processors are to calculate the parameter z based on:

z ={SFN′ y1,y2,y3,y4,y5 +PCI 1,2,3,4,5 +PCI 5,6,7,8,9 } mod N ; and

SFN′=floor[(SFN+eFrame×1024)/8],

where N is the total number of frequency channels, eFrame is the least significant 3 bits of a hyperframe index, the notation of X N1,N2,N3,N4,N5 denotes the N1 th , N2 th , N3 th , N4 th and N5 th least significant bits of parameter X in binary form, parameters y1, y2, y3, y4 and y5 are elements in a permutation of {1, 2, 3, 4, 5}, and floor denotes a flooring function.

13. The apparatus as claimed in claim 12 , wherein the one or more processors are to set the parameter y5 to 5.

14. The apparatus as claimed in claim 12 , wherein the one or more processors are to set the parameters y1, y2, y3, y4 and y5 to two different permutations of {1, 2, 3, 4, 5} when the total number of frequency channels is 16 and when the total number of frequency channels is 32, respectively.

15. The apparatus as claimed in claim 12 , wherein the one or more processors are to determine values respectively of the parameters y1, y2, y3, y4 and y5 according to at least two bits of the SFN.

16. The apparatus as claimed in claim 15 , wherein the one or more processors are to determine the values of the parameters y1, y2, y3, y4 and y5 by a circular shift of a predetermined sequence according to at least two bits of the SFN.

17. An apparatus for generating a frequency hopping sequence in an unlicensed Internet-of-Things (IoT) system, the apparatus comprising: a baseband circuitry that includes:

one or more processors to generate a frequency hopping sequence by conducting a permutation operation based on a physical cell identifier (PCI) and a system frame number (SFN), and to select a channel within an unlicensed spectrum according to the frequency hopping sequence; and

a memory interface to receive data identifying at least one of the PCI or the SFN,

wherein the one or more processors are to generate all possible permutations of indices respectively of frequency channels, to select a predetermined number of unique sequences from the possible permutations, and to generate the frequency hopping sequence based on the unique sequences.

18. The apparatus as claimed in claim 17 , wherein the one or more processors are to generate the possible permutations of the frequency channels as a matrix with dimension (N×N!), where N is the total number of the frequency channels, and to select each of the unique sequences by selecting a specific element of the matrix according to the PCI and the SFN.

19. The apparatus as claimed in claim 18 , wherein the one or more processors are to generate the frequency hopping sequence expressed by:

ψ{[PCI+floor(SFN′/|Φ|)] mod N+ 1,SFN′ mod|Φ|+1},

where ψ is the matrix of possible permutations of the frequency channels, SFN′=floor[(SFN+eFrame×1024)/8], eFrame is the least significant 3 bits of a hyperframe index, |Φ| denotes dimension of the frequency hopping sequence, and floor denotes a flooring function.

20. A non-transitory computer-readable storage medium that stores instructions for execution by one or more processors of an apparatus for generating a frequency hopping sequence, the operations to configure the one or more processors to:

generate a frequency hopping sequence by conducting a permutation operation based on a physical cell identifier (PCI) and a system frame number (SFN);

select a channel within an unlicensed spectrum according to the frequency hopping sequence;

receive data identifying at least one of the PCI or the SFN at a memory interfaces;

conduct a 4-bit permutation operation on four input bits with eight control bits to generate an output sequence with four bits, the 4-bit permutation operation having 4 stages each including 2 cells, each cell to permute two of the input bits by swapping the two of the input bits or directly outputting the two of the input bits; and

generate the frequency hopping sequence based on the output sequence.