Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus
A comparator in an AD conversion part, under the control of a reading part, performs a first comparison processing outputting a digitized first comparison result signal with respect to a voltage signal corresponding to an overflow charge overflowing from a photodiode PD 1 to FD 1 in an integration period and performs a second comparison processing outputting a digitized second comparison result signal with respect to a voltage signal corresponding to an accumulated charge of the photodiode PD 1 transferred to the FD 1 after a transfer period after the integration period, and a signal processing part performs combinational processing applying FWC information and joining a first AD conversion transfer curve TC 1 corresponding to the first comparison processing and a second AD conversion transfer curve TC 2 corresponding to the second comparison processing. Thus, it is possible to smoothly switch (connect) a plurality of signals to be combined and to suppress deterioration of an image.
1. A solid-state imaging device, comprising
a pixel part in which pixels for performing photoelectric conversion are arranged,
a reading circuit which reads out pixel signals from the pixels in the pixel part, and
a processor which combines a plurality of read-out signals to generate a combined signal having an expanded dynamic range, wherein
each pixel includes
a photodiode which accumulates a charge generated by photoelectric conversion in an integration period,
a transistor capable of transferring the charge accumulated in the photodiode in a transfer period after the integration period,
an output node to which the charge accumulated in the photodiode is transferred through the transistor,
an output buffer circuit which converts the charge at the output node to a voltage signal corresponding to a quantity of the charge and outputs the converted voltage signal,
a comparator which performs comparison processing for comparing the voltage signal of the output buffer circuit and a reference voltage and outputting a digitized comparison result signal, and
a memory part for storing data corresponding to the comparison result signal of the comparator,
the comparator, under control of the reading circuit, performs
a first comparison processing for outputting a digitized first comparison result signal with respect to the voltage signal corresponding to an overflow charge overflowing from the photodiode to the output node in the integration period and
a second comparison processing for outputting a digitized second comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photodiode transferred to the output node in the transfer period after the integration period, and
the processor performs combinational processing for joining a first analog-to-digital (AD) conversion transfer curve corresponding to the first comparison processing and a second AD conversion transfer curve corresponding to the second comparison processing.
2. The solid-state imaging device according to claim 1 , wherein:
the processor, in the combinational processing, applies full well capacity (FWC) information of measured pixels and corrects a joining gap between the first AD conversion transfer curve and the second AD conversion transfer curve.
3. The solid-state imaging device according to claim 2 , wherein:
the applied FWC information is at least FWC information obtained in the second comparison processing.
4. The solid-state imaging device according to claim 2 , wherein:
the reference voltage input to the comparator is a linear ramp shaped reference voltage with a step size of a single value, and
the processor performs offset adjustment for shifting a minimum value of the first AD conversion transfer curve according to the first comparison processing in the joining part which is acquired, to a maximum value of the second AD conversion transfer curve according to the second comparison processing in the joining part which is acquired, to thereby join the first AD conversion transfer curve and the second AD conversion transfer curve.
5. The solid-state imaging device according to claim 4 , wherein:
the processor shifts a minimum AD conversion code of the first AD conversion transfer curve according to the first comparison processing in the joining part which is acquired, to a maximum AD conversion code of the second AD conversion transfer curve according to the second comparison processing in the joining part which is acquired, to thereby join the first AD conversion transfer curve and the second AD conversion transfer curve.
6. The solid-state imaging device according to claim 2 , wherein:
the reference voltage input to the comparator is a modulated ramp shaped reference voltage with a step size which does not take a single value, but may continuously change, and
the processor performs offset adjustment for shifting a minimum value of the first AD conversion transfer curve according to the first comparison processing in the joining part which is acquired, to a maximum value of the second AD conversion transfer curve according to the second comparison processing in the joining part which is acquired, and performs non-linear gain correction for adjusting a gain corresponding to the step size according to digital-to-digital re-conversion, to thereby join the first AD conversion transfer curve and the second AD conversion transfer curve.
7. The solid-state imaging device according to claim 6 , wherein:
the processor shifts a minimum AD conversion code of the first AD conversion transfer curve according to the first comparison processing in the joining part which is acquired, to a maximum AD conversion code of the second AD conversion transfer curve according to the second comparison processing in the joining part which is acquired, and re-converts, in the digital-to-digital re-conversion, the minimum AD conversion code and the maximum AD conversion code in the digital region to match with a desired transfer curve to thereby join the first AD conversion transfer curve and the second AD conversion transfer curve.
8. The solid-state imaging device according to claim 7 , wherein:
the processor performs the digital-to-digital re-conversion for the minimum AD conversion code and the maximum AD conversion code by using a correction coefficient related to the FWC information for each pixel of the digital region.
9. The solid-state imaging device according to claim 6 , wherein:
the modulated ramp shaped reference voltage is generated so that a ramp waveform is linear and an AD conversion code step is modulated.
10. The solid-state imaging device according to claim 6 , wherein:
the modulated ramp shaped reference voltage is generated by changing a ramp waveform and making an AD conversion code step linear.
11. The solid-state imaging device according to claim 2 , wherein:
the reference voltage input to the comparator is a linear ramp shaped reference voltage with a step size of a single value, and
the processor performs offset adjustment for shifting a minimum value of the first AD conversion transfer curve according to the first comparison processing in the joining part which is acquired, to a maximum value of the second AD conversion transfer curve according to the second comparison processing in the joining part which is acquired, and performs non-linear gain correction adjusting a gain corresponding to the step size according to digital-to-digital re-conversion, to thereby join the first AD conversion transfer curve and the second AD conversion transfer curve.
12. The solid-state imaging device according to claim 11 , wherein:
the processor shifts a minimum AD conversion code of the first AD conversion transfer curve according to the first comparison processing in the joining part which is acquired, to a maximum AD conversion code of the second AD conversion transfer curve according to the second comparison processing in the joining part which is acquired, and re-converts, in the digital-to-digital re-conversion, the AD conversion code in the digital region to match with a desired transfer curve, to thereby join the first AD conversion transfer curve and the second AD conversion transfer curve.
13. The solid-state imaging device according to claim 12 , wherein:
the processor performs the digital-to-digital re-conversion for the minimum AD conversion code and the maximum AD conversion code by using a correction coefficient related to the FWC information for each pixel of the digital region.
14. The solid-state imaging device according to claim 2 , wherein:
the FWC information is measured from a result obtained by performing the first comparison processing and then performing the second comparison processing using a ramp shaped reference voltage which is not modulated, in an on line state where the solid-state imaging device is normally operating.
15. The solid-state imaging device according to claim 2 , wherein:
the FWC information is information measured in advance by driving the pixels in an off line state where the solid-state imaging device is not normally operating.
16. The solid-state imaging device according to claim 1 , wherein:
the comparator, in the first comparison processing,
outputs the first comparison result signal corresponding to a time in accordance with a quantity of the overflow charge and
handles a light level from a signal level of the photodiode in a maximum sampling time at which the overflow charge begins to overflow from the photodiode to the output node to a signal level obtained in a minimum sampling time.
17. The solid-state imaging device according to claim 1 , wherein:
the integration period is a period from when the photodiode and the output node are reset to a reset level to when the transistor is switched to a conductive state and the transfer period is started,
a period of the first comparison processing is a period from when the photodiode and the output node are reset to the reset level to when the output node is reset to the reset level before the transfer period is started, and
a period of the second comparison processing is a period after the output node is reset to the reset level and is a period including the period after the transfer period.
18. The solid-state imaging device according to claim 1 , wherein:
the device includes
a first substrate and
a second substrate,
the first substrate and the second substrate have a stacked structure where these substrates are connected through a connection part,
at least the photodiode, the transistor, the output node, and the output buffer circuit in the pixel are formed on the first substrate, and
at least the comparator, the memory part, and at least a portion of the reading circuit are formed on the second substrate.
19. A method for driving a solid-state imaging device having
a pixel part in which pixels for performing photoelectric conversion are arranged,
a reading circuit which reads out pixel signals from the pixels in the pixel part, and
a processor which combines a plurality of read-out signals to generate a combined signal having an expanded dynamic range, wherein
each pixel includes
a photodiode which accumulates a charge generated by photoelectric conversion in an integration period,
a transistor capable of transferring the charge accumulated in the photodiode in a transfer period after the integration period,
an output node to which the charge accumulated in the photodiode is transferred through the transistor,
an output buffer circuit which converts the charge at the output node to a voltage signal corresponding to a quantity of the charge and outputs the converted voltage signal,
a comparator which performs comparison processing for comparing the voltage signal of the output buffer circuit and a reference voltage and outputting a digitized comparison result signal, and
a memory part for storing data corresponding to the comparison result signal of the comparator,
the method for driving a solid-state imaging device comprising:
when reading out pixel signals of the pixels,
by means of the comparator, under control of the reading circuit,
performing a first comparison processing for outputting a digitized first comparison result signal with respect to the voltage signal corresponding to an overflow charge overflowing from the photodiode to the output node in the integration period, and
performing a second comparison processing for outputting a digitized second comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photodiode transferred to the output node in the transfer period after the integration period, and
by means of the processor, performing combinational processing for joining a first analog-to-digital (AD) conversion transfer curve corresponding to the first comparison processing and a second AD conversion transfer curve corresponding to the second comparison processing.
20. An electronic apparatus, comprising
a solid-state imaging device and
a lens for forming a subject image in the solid-state imaging device, wherein
the solid-state imaging device has
a pixel part in which pixels for performing photoelectric conversion are arranged,
a reading circuit which reads out pixel signals from the pixels in the pixel part, and
a processor which combines a plurality of read-out signals to generate a combined signal having an expanded dynamic range,
each pixel includes
a photodiode which accumulates a charge generated by photoelectric conversion in an integration period,
a transistor capable of transferring the charge accumulated in the photodiode in a transfer period after the integration period,
an output node to which the charge accumulated in the photodiode is transferred through the transistor,
an output buffer circuit which converts the charge at the output node to a voltage signal corresponding to a quantity of the charge and outputs the converted voltage signal,
a comparator which performs comparison processing for comparing the voltage signal of the output buffer circuit and a reference voltage and outputting a digitized comparison result signal, and
a memory part for storing data corresponding to the comparison result signal of the comparator,
the comparator, under control of the reading circuit,
performs a first comparison processing for outputting a digitized first comparison result signal with respect to the voltage signal corresponding to an overflow charge overflowing from the photodiode to the output node in the integration period, and
performs a second comparison processing for outputting a digitized second comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photodiode transferred to the output node in the transfer period after the integration period, and
the processor performs combinational processing for joining a first analog-to-digital (AD) conversion transfer curve corresponding to the first comparison processing and a second AD conversion transfer curve corresponding to the second comparison processing.