Semiconductor memory device and operating method thereof
View Patent ↗A semiconductor memory device including a memory cell array including a plurality of memory blocks, a voltage generator applying operation voltages to a selected memory block, among the plurality of memory blocks, a control logic generating converted data by converting data bit sets respectively corresponding to at least one set of program states among a plurality of program states, during a program operation, and a read and write circuit temporarily storing the converted data and performing a program operation by controlling potential levels of bit lines of the memory cell array in accordance with stored converted data.
1. A semiconductor memory device comprising:
a memory cell array comprising a plurality of memory cells;
a peripheral circuit configured to perform a program operation to store converted data in selected memory cells among the plurality of memory cells; and
a control logic configured to generate the converted data from original data by reducing a number of program states for the original data to a lower number of program states for the converted data, wherein the number of program states for the original data is at least two, and configured to control the peripheral circuit to store the converted data in the selected memory cells.
2. The semiconductor memory device of claim 1 ,
wherein the program states for the converted data represent a subset of the program states for the original data.
3. The semiconductor memory device of claim 2 ,
wherein a program state for the original data absent from the converted data represents a highest program state among the program states for the original data.
4. The semiconductor memory device of claim 2 , wherein the control logic comprises:
a data conversion circuit configured to generate the converted data by inverting at least one data bit of a data bit set of a program state for the original data absent from the converted data; and
a register circuit configured to store conversion address information,
wherein the conversion address information comprises an address for the selected memory cells.
5. The semiconductor memory device of claim 4 , wherein the at least one data bit is a least significant bit.
6. The semiconductor memory device of claim 4 , wherein the at least one data bit is a most significant bit.
7. The semiconductor memory device of claim 4 ,
wherein the data conversion circuit is configured to generate the converted data by changing a first data bit set corresponding to a first program state among the program states for the original data to a second data bit set corresponding to a second program state among the program states for the converted data,
wherein the second program state is absent from the program states for the original data, and
wherein the second program state has a lower threshold voltage distribution than the first program state.
8. The semiconductor memory device of claim 4 ,
wherein the data conversion circuit is configured to restore the original data from the converted data when the converted data is read from the selected memory cells.
9. The semiconductor memory device of claim 4 ,
wherein the data conversion circuit is configured to restore the original data from the converted data based on the conversion address information.
10. The semiconductor memory device of claim 4 ,
wherein the data conversion circuit is configured to generate the conversion address information during the program operation.
11. The semiconductor memory device of claim 1 ,
wherein the peripheral circuit is configured to include a read and write circuit to store the converted data temporarily, and
wherein the control logic is configured to include a control signal generator which generates a control signal that controls the read and write circuit to store the converted data on the selected memory cells.
12. A method of operating a semiconductor memory device comprising a plurality of memory cells, the method comprising:
receiving original data;
generating converted data from the original data by reducing a number of program states for the original data to a lower number of program states for the converted data, wherein the number of program states for the original data is at least two; and
performing a program operation to store the converted data in selected memory cells among the plurality of memory cells.
13. The method of claim 12 ,
wherein the program states for the converted data represent a subset of the program states for the original data.
14. The method of claim 13 ,
wherein a program state for the original data absent from the converted data represents a highest program state among the program states for the original data.
15. The method of claim 13 , wherein the generating the converted data comprises inverting at least one data bit of a data bit set of a program state for the original data absent from the converted data.
16. The method of claim 15 ,
wherein the at least one data bit is a least significant bit or a most significant bit.
17. The method of claim 13 , wherein the generating the converted data comprises changing a first data bit set corresponding to a first program state among the program states for the original data to a second data bit set corresponding to a second program state among the program states for the converted data,
wherein the second program state is absent from the program states for the original data, and
wherein the second program state has a lower threshold voltage distribution than the first program state.
18. The method of claim 12 , further comprising storing conversion address information which comprises an address for the selected memory cells.
19. The method of claim 18 , further comprising restoring the original data from the converted data when the converted data is read from the selected memory cells.
20. The method of claim 19 , wherein the original data is restored from the converted data based on the conversion address information.