Memory device for performing a selective erase operation and memory system having the same
Provided herein may be a memory device and a memory system including the memory device. The memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to perform a selective erase operation on the memory cells, and control logic configured to control, during the selective erase operation, the peripheral circuit to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a selected string among a plurality of strings in the memory block, and float unselected word lines and unselected strings.
1. A memory device comprising:
a memory block including a plurality of memory cells; and
a peripheral circuit configured to perform a selective erase operation on the memory cells in a string basis,
wherein, during the selective erase operation, the peripheral circuit is configured to apply an erase voltage to a bit line coupled to a selected string of a plurality of strings coupled to different bit lines among a plurality of bit lines in the memory block and float unselected strings.
2. The memory device according to claim 1 ,
wherein the plurality of strings are coupled between the plurality of bit lines and a source line, and
wherein each of the strings comprises a drain select transistor, a plurality of memory cells, and a source select transistor.
3. The memory device according to claim 2 , wherein a positive voltage is applied to the source line, and a floating voltage is applied to bit lines coupled to the unselected strings.
4. The memory device according to claim 3 , wherein, after all of the source select transistors in the memory block are turned off and all of the drain select transistors in the memory block are turned on, drain select transistors in the unselected strings are turned off by the floating voltage.
5. The memory device according to claim 1 , wherein an erase allowable voltage is applied to all word lines in the memory block.
6. A memory device comprising:
a memory block including a plurality of memory cells; and
a peripheral circuit configured to perform a selective erase operation on the memory cells in a memory cell basis,
wherein, during the selective erase operation, the peripheral circuit is configured to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a bit line coupled to a selected string among a plurality of strings coupled to different bit lines among a plurality of bit lines in the memory block, and float unselected word lines and unselected strings.
7. The memory device according to claim 6 ,
wherein the plurality of strings are coupled between the plurality of bit lines and a source line, and
wherein each of the strings comprises a drain select transistor, a plurality of memory cells, and a source select transistor.
8. The memory device according to claim 7 , wherein a positive voltage is applied to the source line, and a floating voltage is applied to bit lines coupled to the unselected strings.
9. The memory device according to claim 8 , wherein, after all of the source select transistors in the memory block are turned off and all of the drain select transistors in the memory block are turned on, drain select transistors in the unselected strings are turned off by the floating voltage.
10. A memory system comprising:
a memory device including a memory block; and
a memory controller configured to output a select erase command and an address of a selected memory cell, among a plurality of memory cells in the memory block,
wherein the memory device is configured to perform a selective erase operation in a string basis or a memory cell basis according to the select erase command and the address, and inhibit erasure of unselected memory cells by floating some word lines and strings, among all word lines and strings, in the memory block,
wherein the strings are coupled to different bit lines among a plurality of bit lines, and
wherein an erase voltage is applied to a bit line coupled to a selected string among the strings.
11. The memory system according to claim 10 , wherein, during the selective erase operation in the string basis, an erase allowable voltage is applied to all word lines in the memory block, and a floating voltage is applied to bit lines coupled to unselected strings.
12. The memory system according to claim 10 , wherein, during the selective erase operation in the memory cell basis, an erase allowable voltage is applied to a selected word line among the word lines, a floating voltage is applied to unselected word lines, and a floating voltage is applied to bit lines coupled to unselected strings.