Resource utilization of heterogeneous compute units in electronic design automation

1. A method performed by a computing system, the method comprising:

identifying a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes a plurality of compute units with differing computing capabilities;

identifying an EDA operation to be performed for the EDA application;

selecting a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit; and

assigning an execution of the EDA operation to the selected compute unit,

wherein the determined computing capability comprises a performance benchmark for the EDA operation specific to the selected compute unit, and further comprising obtaining, for different EDA operations, performance benchmarks for the plurality of compute units included in the pool of heterogeneous compute units, including by:

issuing benchmark operations specific to the different EDA operations to each of the plurality of compute units included in the pool of heterogeneous compute units; and

tracking performance of each of the plurality of compute units in executing the issued benchmark operations.

2. The method of claim 1 , wherein the determined computing capability further comprises a threshold number of central processing units (CPUs), a threshold processor speed, a threshold memory speed, or a threshold amount of available memory.

3. The method of claim 1 , wherein the selecting comprises:

identifying a particular computing capability relevant to the EDA operation; and

selecting a particular compute unit from among the pool of heterogeneous compute units with a highest measure of the particular computing capability.

4. The method of claim 1 , wherein the EDA operation is a design-rule-check (DRC) operation; and

wherein the selecting comprises selecting a particular compute unit among the pool of heterogeneous compute units to perform the DRC operation with a highest processor speed, a highest cache memory speed, or a combination of both.

5. The method of claim 1 , wherein the EDA operation is a lithography operation; and

wherein the selecting comprises selecting a particular compute unit among the pool of heterogeneous compute units to perform the lithography operation with a highest main memory speed.

6. The method of claim 1 , comprising obtaining the performance benchmarks for the plurality of compute units and selecting the computing unit among the pool of heterogeneous compute units to execute the EDA operation without determining specific resource configurations of the plurality of computing units.

7. A system comprising:

a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes a plurality of compute units with differing computing capabilities; and

a resource utilization engine configured to:

identify an EDA operation to be performed for the EDA application;

select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit; and

assign an execution of the EDA operation to the selected compute unit,

wherein the determined computing capability comprises a performance benchmark for the EDA operation specific to the selected compute unit, and

wherein the resource utilization engine is further configured to obtain, for different EDA operations, performance benchmarks for the plurality of compute units included in the pool of heterogeneous compute units, including by:

issuing benchmark operations specific to the different EDA operations to each of the plurality of compute units included in the pool of heterogeneous compute units; and

tracking performance of each of the plurality of compute units in executing the issued benchmark operations.

8. The system of claim 7 , wherein the determined computing capability further comprises a threshold number of central processing units (CPUs), a threshold processor speed, a threshold memory speed, or a threshold amount of available memory.

9. The system of claim 7 , wherein the resource utilization engine is configured to select the compute unit by:

identifying a particular computing capability relevant to the EDA operation; and

selecting a particular compute unit from among the pool of heterogeneous compute units with a highest measure of the particular computing capability.

10. The system of claim 7 , wherein:

the EDA operation is a design-rule-check (DRC) operation; and

the resource utilization engine is configured to select a particular compute unit among the pool of heterogeneous compute units to perform the DRC operation with a highest processor speed, a highest cache memory speed, or a combination of both.

11. The system of claim 7 , wherein:

the EDA operation is a lithography operation; and

the resource utilization engine is configured to select a particular compute unit among the pool of heterogeneous compute units to perform the lithography operation with a highest main memory speed.

12. The system of claim 7 , wherein the resource utilization engine is configured to obtain the performance benchmarks for the plurality of compute units and select the computing unit among the pool of heterogeneous compute units to execute the EDA operation without determining specific resource configurations of the plurality of computing units.

13. The system of claim 7 , wherein the performance benchmarks comprise execution latencies for executions of the EDA operation by the plurality of computing units.

14. A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause a system to:

identify a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes a plurality of compute units with differing computing capabilities;

identify an EDA operation to be performed for the EDA application;

select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit; and

assign an execution of the EDA operation to the selected compute unit,

wherein the determined computing capability comprises a performance benchmark for the EDA operation specific to the selected compute unit, and wherein the instructions, when executed by the processor, further cause the system to obtain, for different EDA operations, performance benchmarks for the plurality of compute units included in the pool of heterogeneous compute units, including by:

issuing benchmark operations specific to the different EDA operations to each of the plurality of compute units included in the pool of heterogeneous compute units; and

tracking performance of each of the plurality of compute units in executing the issued benchmark operations.

15. The non-transitory machine-readable medium of claim 14 , wherein the determined computing capability further comprises a threshold number of central processing units (CPUs), a threshold processor speed, a threshold memory speed, or a threshold amount of available memory.

16. The non-transitory machine-readable medium of claim 14 , wherein the instructions to select a compute unit among the pool of heterogeneous compute units comprise instructions that, when executed, cause the system to:

identify a particular computing capability relevant to the EDA operation; and

select a particular compute unit from among the pool of heterogeneous compute units with a highest measure of the particular computing capability.

17. The non-transitory machine-readable medium of claim 14 , wherein:

the EDA operation is a design-rule-check (DRC) operation; and

the instructions to select the compute unit comprise instructions that, when executed, cause the system to select a particular compute unit among the pool of heterogeneous compute units to perform the DRC operation with a highest processor speed, a highest cache memory speed, or a combination of both.

18. The non-transitory machine-readable medium of claim 14 , wherein:

the EDA operation is a lithography operation; and

the instructions to select the compute unit comprise instructions that, when executed, cause the system to select a particular compute unit among the pool of heterogeneous compute units to perform the lithography operation with a highest main memory speed.

19. The non-transitory machine-readable medium of claim 14 , wherein the instructions, when executed by the processor, cause the system to obtain the performance benchmarks for the plurality of compute units and select the computing unit among the pool of heterogeneous compute units to execute the EDA operation without determining specific resource configurations of the plurality of computing units.

20. The non-transitory machine-readable medium of claim 14 , wherein the performance benchmarks comprise execution latencies for executions of the EDA operation by the plurality of computing units.