IP Library Granted Patent US 10,680,619
Granted Patent B2
US 10,680,619 · App. 16/170,716 · Granted Jun 9, 2020

Digital phase locked loop frequency estimation

Inventors: Elan Banin (Raanana, IL); Roy Amel (Haifa, IL); Ran Shimon (Ramat Gan, IL); Ashoke Ravi (Hillsboro, OR); Nati Dinur (Haifa, IL)
Assignee: Intel IP Corporation
H03L7/08H03L7/085H03L9/00H04L27/0014H04L2027/0053H04L2027/0067
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Quick Facts
Patent No.
US 10,680,619
App. No.
16/170,716
Granted
Jun 9, 2020
Kind
B2
Abstract

A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

Claims (158)

1. A Digital Phase Locked Loop (DPLL), comprising:

a Time-to-Digital Converter (TDC) configured to generate quantized phase values of a controlled oscillator signal; and

a frequency estimation circuit configured to receive the quantized phase values, determine a wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

2. The DPLL of claim 1 , wherein the frequency estimation circuit comprises:

a phase determination circuit configured to determine an accumulation of the quantized phase values having the wraparound phase.

3. The DPLL of claim 1 , wherein the frequency estimation circuit comprises:

a wraparound phase determination circuit configured to determine the wraparound phase of the quantized phase values.

4. The DPLL of claim 3 , wherein the wraparound phase determination circuit comprises a decision circuit configured to determine the wraparound phase by comparing a difference between a current quantized phase value and a previous quantized phase value with an expected frequency.

5. The DPLL of claim 4 , wherein the decision circuit determines the wraparound phase in accordance with the following:

L

I

=

{

-

1

,

(

φ

k

-

φ

k

-

1

)

-

f

exp

<

-

P

/

2

0

,

else

1

,

(

φ

k

-

φ

k

-

1

)

-

f

exp

>

P

/

2

}

,

L

=

l

=

1

k

L

l

,

where L is an accumulated number of phase wraparounds, φ k is the current quantized phase value, φ k-1 is the previous quantized phase value, f exp is the expected frequency, k is an index number of a phase value, and P is a threshold proportional to a period of the controlled oscillator signal.

6. The DPLL of claim 5 , wherein the frequency estimation circuit comprises:

an estimated frequency determination circuit configured to determine the estimated frequency by removing the wraparound phase from the quantized phase values.

7. The DPLL of claim 5 , wherein a value of the period used in the wraparound phase determination is an estimate of the period of the controlled oscillator signal.

8. The DPLL of claim 1 , wherein the estimated frequency is represented as follows:

{circumflex over (f)}=b 2 *y k =b 2 *{tilde over (y)} k +b 2 *( L k ·P ),

where {circumflex over (f)} is the estimated frequency, b 2 is a predetermined matrix, * is a multiplication operation of a vector by a vector, y k is a quantized phase value without the wraparound phase, {tilde over (y)} k is a quantized phase value with the wraparound phase, L k is an accumulated number of phase wraparounds, k is an index number of a phase value, and P is a threshold proportional to a period of the controlled oscillator signal.

9. The DPLL of claim 1 , wherein the frequency estimation circuit is configured to estimate the frequency on a quantized phase value-by-quantized phase value basis.

10. The DPLL of claim 1 , wherein the quantized phase values are in units relative to a period of the controlled oscillator signal.

11. A wireless communication device, comprising:

a baseband processor comprising the DPLL of claim 1 , or

a Radio Frequency (RF) front end comprising the DPLL of claim 1 .

12. A method of operating a Digital Phase Locked Loop (DPLL), comprising:

generating, by a Time-to-Digital Converter (TDC), quantized phase values of a controlled oscillator signal;

determining, by a frequency estimation circuit, a wraparound phase of the quantized phase values; and

least-squares estimating, by the frequency estimation circuit, a frequency based on the quantized phase values and the wraparound phase.

13. The method of claim 12 , wherein the least-squares estimating comprises:

determining, by a phase determination circuit, an accumulation of the quantized phase values having the wraparound phase.

14. The method of claim 12 , wherein the wraparound phase of the quantized phase values is determined by a wraparound phase determination circuit comprised within the frequency estimation circuit.

15. The method of claim 14 , wherein the wraparound phase is determined by a decision circuit comprised within the wraparound phase determination circuit, and by comparing a difference between a current quantized phase value and a previous quantized phase value with an expected frequency.

16. The method of claim 15 , wherein the decision circuit determines the wraparound phase is in accordance with the following:

L

I

=

{

-

1

,

(

φ

k

-

φ

k

-

1

)

-

f

exp

<

-

P

/

2

0

,

else

1

,

(

φ

k

-

φ

k

-

1

)

-

f

exp

>

P

/

2

}

,

L

=

l

=

1

k

L

l

.

where L is an accumulated number of phase wraparounds, φ k is the current quantized phase value, φ k-1 is the previous quantized phase value, f exp is an expected frequency, k is an index number of a phase value, and P is a threshold proportional to a period of the controlled oscillator signal.

17. The method of claim 16 , wherein a value of the period used in the wraparound phase determination is an estimate of the period of the controlled oscillator signal.

18. The method of claim 12 , wherein the least-squares estimating comprises:

determining, by an estimated frequency determination circuit within the frequency estimation circuit, the estimated frequency by removing the wraparound phase from the quantized phase values.

19. The method of claim 12 , wherein the estimated frequency is represented as follows:

{circumflex over (f)}=b 2 *y k =b 2 *{tilde over (y)} k +b 2 *( L k ·P ),

where {circumflex over (f)} is the estimated frequency, b 2 is a predetermined matrix, * is a multiplication operation of a vector by a vector, y k is a quantized phase value without wraparound phase, {tilde over (y)} k is a quantized phase value with wraparound phase, L k is an accumulated number of phase wraparounds, k is an index number of a phase value, and P is a threshold proportional to a period of the controlled oscillator signal.

20. The method of claim 12 , wherein the least-squares frequency estimating comprises:

estimating the frequency on a quantized phase value-by-quantized phase value basis.

21. The method of claim 12 , wherein the quantized phase values are in units relative to a period of the controlled oscillator signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057061/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057254/0415 →