Lane reversal detection and bifurcation system
A lane reversal detection and bifurcation system includes an interface that includes a plurality of lanes that are coupled to an endpoint interface of an endpoint device and a BIOS that bifurcates the interface into a first root port and a second root port, such that the first root port is coupled to a first subset of the plurality of lanes, and the second root port is coupled to a second subset of the plurality of lanes. The BIOS initializes the endpoint device to establish a link between the endpoint device and the interface. The BIOS detects an endpoint presence and a non-functional link at the first root port and an endpoint presence and a functional link at the second root port and, in response, determines that the first subset of the plurality of lanes coupled to the endpoint device are subject to a lane reversal.
1. A lane reversal detection and bifurcation system, comprising:
a chassis;
a chassis interface that is accessible on the chassis and that includes a plurality of lanes;
a first endpoint device that includes a first endpoint interface that is coupled to the chassis interface; and
a Basic Input/Output System (BIOS) that is provided in the chassis and that is coupled to the chassis interface, and wherein the BIOS is configured to:
bifurcate the chassis interface into a first root port and a second root port, wherein the first root port is coupled to a first subset of the plurality of lanes, and where the second root port is coupled to a second subset of the plurality of lanes, wherein the first endpoint device is coupled to the first subset of the plurality of lanes and the second subset of the plurality of lanes;
initialize the first endpoint device to establish a link between the first endpoint device and the chassis interface;
detect an endpoint presence and a non-functional link at the first root port;
detect an endpoint presence and a functional link at the second root port; and
determine, in response to the detecting the endpoint presence and the non-functional link at the first root port and the detecting the endpoint presence and the functional link at the second root port, that the first subset of the plurality of lanes coupled to the first endpoint device are subject to a lane reversal.
2. The system of claim 1 , wherein the determining that the first subset of the plurality of lanes coupled to the first endpoint device are subject to a lane reversal is also in response to determining that the first subset of the plurality of lanes included on the first root port and the second subset of the plurality of lanes included on the second root port are adjacent each other, and the first subset of the plurality of lanes and the second subset of the plurality of lanes correspond with a link width capability of the first endpoint device.
3. The system of claim 1 , wherein the BIOS is further configured to:
bifurcate the chassis interface based on the first subset of the plurality of lanes coupled to the first endpoint device being subject to the lane reversal.
4. The system of claim 1 , wherein the BIOS is further configured to:
bifurcate, based on the first subset of the plurality of lanes coupled to the first endpoint device being subject to the lane reversal, the chassis interface into a third root port that includes the first subset of the plurality of lanes and the second subset of the plurality of lanes.
5. The system of claim 4 , wherein the BIOS is further configured to:
bifurcate, based on the first subset of the plurality of lanes coupled to the first endpoint device being subject to the lane reversal, the chassis interface into a fourth root port that includes at least a third subset of the plurality of lanes.
6. The system of claim 1 , wherein the BIOS is further configured to:
clear a presence detect change bit of a chassis interface register prior to the initializing the first endpoint device to establish the link between the first endpoint device and the chassis interface, wherein the detecting the endpoint presence of the first endpoint device at the first root port includes detecting the presence detect change bit.
7. The system of claim 1 , wherein the chassis interface is a Peripheral Component Interconnect (PCI) Express (PCIe) interface, and wherein the first endpoint device is a first PCIe device.
8. The system of claim 1 , wherein the first subset of the plurality of lanes is equal to the second subset of the plurality of lanes.
9. An information handling system (IHS), comprising:
an interface that includes a plurality of lanes;
a processing subsystem coupled to the interface; and
a memory subsystem that is coupled to the processing subsystem and that includes instructions that, when executed by the processing subsystem, causes the processing subsystem to provide a Basic Input/Output System (BIOS) that is configured to:
bifurcate the interface into a first root port and a second root port, wherein the first root port is coupled to a first subset of the plurality of lanes, and where the second root port is coupled to a second subset of the plurality of lanes;
initialize an endpoint device that includes an endpoint interface that is coupled to the interface to establish a link between the endpoint device and the interface;
detect an endpoint presence and a non-functional link at the first root port;
detect an endpoint presence and a functional link at the second root port; and
determine, in response to the detecting the endpoint presence and the non-functional link at the first root port and the detecting the endpoint presence and the functional link at the second root port, that the first subset of the plurality of lanes coupled to the endpoint device are subject to a lane reversal.
10. The IHS of claim 9 , wherein the determining that the first subset of the plurality of lanes coupled to the endpoint device are subject to a lane reversal is also in response to determining that the first subset of the plurality of lanes included on the first root port and the second subset of the plurality of lanes included on the second root port are adjacent each other, and the first subset of the plurality of lanes and the second subset of the plurality of lanes correspond with a link width capability of the endpoint device.
11. The IHS of claim 9 , wherein the BIOS is further configured to:
bifurcate the interface based on the first subset of the plurality of lanes coupled to the endpoint device being subject to the lane reversal.
12. The IHS of claim 9 , wherein the BIOS is further configured to:
bifurcate, based on the first subset of the plurality of lanes coupled to the endpoint device being subject to the lane reversal, the interface into a third root port that includes the first subset of the plurality of lanes and the second subset of the plurality of lanes.
13. The IHS of claim 12 , wherein the BIOS is further configured to:
bifurcate, based on the first subset of the plurality of lanes coupled to the endpoint device being subject to the lane reversal, the interface into a fourth root port that includes at least a third subset of the plurality of lanes.
14. The IHS of claim 9 , wherein the BIOS is further configured to:
clear a presence detect change bit of an interface register prior to the initializing the endpoint device to establish the link between the endpoint device and the interface, wherein the detecting the endpoint presence of the endpoint device at the first root port includes detecting the presence detect change bit.
15. The IHS of claim 9 , wherein the first subset of the plurality of lanes is equal to the second subset of the plurality of lanes.
16. A method of detecting a lane reversal, comprising:
bifurcating, by a Basic Input/Output System (BIOS), an interface having a plurality of lanes into a first root port and a second root port, wherein the first root port is coupled to a first subset of the plurality of lanes, and where the second root port is coupled to a second subset of the plurality of lanes;
initializing, by the BIOS, an endpoint device that includes an endpoint interface that is coupled to the interface to establish a link between the endpoint device and the interface;
detecting, by the BIOS, an endpoint presence and a non-functional link at the first root port;
detecting, by the BIOS, an endpoint presence and a functional link at the second root port; and
determining, by the BIOS and in response to the detecting the endpoint presence and the non-functional link at the first root port and the detecting the endpoint presence and the functional link at the second root port, that the first subset of the plurality of lanes coupled to the endpoint device are subject to a lane reversal.
17. The method of claim 16 , wherein the determining that the first subset of the plurality of lanes coupled to the endpoint device are subject to a lane reversal is also in response to determining that the first subset of the plurality of lanes included on the first root port and the second subset of the plurality of lanes included on the second root port are adjacent each other, and the first subset of the plurality of lanes and the second subset of the plurality of lanes correspond with a link width capability of the endpoint device.
18. The method of claim 16 , further comprising:
bifurcating, by the BIOS, the interface based on the first subset of the plurality of lanes coupled to the endpoint device being subject to the lane reversal.
19. The method of claim 16 , further comprising:
bifurcating, by the BIOS and based on the first subset of the plurality of lanes coupled to the endpoint device being subject to the lane reversal, the interface into a third root port that includes the first subset of the plurality of lanes and the second subset of the plurality of lanes.
20. The method of claim 16 , further comprising:
clear a presence detect change bit of an interface register prior to the initializing the endpoint device to establish the link between the endpoint device and the interface, wherein the detecting the endpoint presence of the endpoint device at the first root port includes detecting the presence detect change bit.