Correlated addresses and prefetching
An apparatus is provided that includes cache circuitry that comprises a plurality of cache lines. The cache circuitry treats one or more of the cache lines as trace lines each having correlated addresses and each being tagged by a trigger address. Prefetch circuitry causes data at the correlated addresses stored in the trace lines to be prefetched.
1. An apparatus comprising:
cache circuitry comprising a plurality of cache lines each configured to store data, wherein the cache circuitry is configured to treat one or more of the cache lines as trace lines, wherein each trace line in the trace lines is tagged by a trigger address and comprises one or more correlated addresses as the data of the trace line that are correlated to and different to the trigger address; and
prefetch circuitry configured to cause data at the correlated addresses stored in the trace lines to be prefetched,
wherein each line in the plurality of cache lines comprises at least one flag to indicate whether that line is one of the trace lines,
wherein the at least one flag includes a c flag and a d flag to indicate whether that line is one of the trace lines and the c flag and the d flag are mutually-exclusive,
the apparatus further comprising eviction circuitry to evict the plurality of cache lines from the cache circuitry in dependence on one or more standard eviction conditions,
wherein the eviction circuitry is configured to inhibit evicting the trace lines in dependence on one or more correlated-address eviction conditions.
2. An apparatus according to claim 1 , wherein
the prefetch circuitry is configured to cause the data at the correlated addresses to be prefetched in response to the trigger address being accessed.
3. An apparatus according to claim 1 , comprising:
obtaining circuitry configured to obtain the correlated addresses, wherein
the correlated addresses relate to data where a miss has occurred.
4. An apparatus according to claim 1 , wherein
the correlated addresses relate to data that has been explicitly fetched.
5. An apparatus according to claim 1 , wherein
the correlated addresses relate to data that has been fetched as part of a load operation.
6. An apparatus according to claim 1 , wherein
the correlated addresses contain at least one storage location where another of the correlated addresses is stored.
7. An apparatus according to claim 1 , wherein
the trigger address and the correlated addresses form a linked list.
8. An apparatus according to claim 1 , wherein
the correlated addresses in each of the trace lines are compressed.
9. An apparatus according to claim 8 , wherein
the correlated addresses in a given trace line are compressed by storing a base address and, for each individual address in the correlated addresses of the given trace line, a delta between the base address and the individual address.
10. An apparatus according to claim 9 , wherein
the base address comprises common bits between the plurality of correlated addresses in the given trace line; and
the delta comprises remaining bits from the individual address when the common bits are removed.
11. An apparatus according to claim 1 , wherein
the one or more correlated-address eviction conditions includes a fill condition;
the plurality of cache lines are grouped into a plurality of sets;
each set in the plurality of sets has a set counter, which is incremented in response to a fill being made to that set; and
the fill condition causes a given trace line in the set to be made evictable based on the set counter associated with the given trace line.
12. An apparatus according to claim 11 , wherein
the given trace line in the set is associated with a line counter;
the line counter is incremented each time the set counter of the given line reaches a predetermined value; and
the fill condition causes the given line to be made evictable when the line counter reaches a further predetermined value.
13. An apparatus according to claim 12 , comprising:
trigger queue circuitry to store a plurality of triggering addresses, wherein
in response to the trigger address of the given line missing when the trigger queue circuitry is at its maximum capacity, the line counter associated with the given line is incremented.
14. An apparatus according to claim 12 , wherein
the one or more correlated-address eviction conditions includes a double-hit condition;
the double-hit condition causes a given trace line to be made evictable in response to the cache circuitry hitting, in response to a request, on both the given cache line and a further cache line that is other than one of the trace lines; and
the given cache line and the further cache line have a same tag.
15. An apparatus according to claim 14 , wherein
in response to adding a new trace line when the cache contains the further cache line that is other than one of the trace lines, the further cache line is marked as being evictable.
16. An apparatus according to claim 1 , wherein
the cache circuitry is configured to limit a number of the trace lines to a predetermined level.
17. A method comprising:
storing a plurality of cache lines each storing data, the cache lines including one or more trace lines tagged by a trigger address and each comprising correlated addresses as the data of the trace line that are correlated to and different to the trigger address;
causing data at the correlated addresses stored in the trace lines to be prefetched,
wherein each line in the plurality of cache lines comprises at least one flag to indicate whether that line is one of the trace lines,
wherein the at least one flag includes a c flag and a d flag to indicate whether that line is one of the trace lines and the c flag and the d flag are mutually-exclusive, the method further comprising:
evicting the plurality of cache lines from the cache circuitry in dependence on one or more standard eviction conditions; and
inhibiting eviction of the trace lines in dependence on one or more correlated-address eviction conditions.
18. An apparatus comprising:
means for storing a plurality of cache lines each configured to store data, the cache lines including one or more trace lines tagged by a trigger address and each comprising correlated addresses as the data of the trace line that are correlated to and different to the trigger address; and
means for causing data at the correlated addresses stored in the trace lines to be prefetched,
wherein each line in the plurality of cache lines comprises at least one flag to indicate whether that line is one of the trace lines,
wherein the at least one flag includes a c flag and a d flag to indicate whether that line is one of the trace lines and the c flag and the d flag are mutually-exclusive,
the apparatus further comprising means for evicting the plurality of cache lines from the cache circuitry in dependence on one or more standard eviction conditions,
wherein the means for evicting is configured to inhibit evicting the trace lines in dependence on one or more correlated-address eviction conditions.