System and method of utilizing different memory media with a device
View Patent ↗In one or more embodiments, one or more methods, processes, and/or systems may receive quality of service (QoS) configuration information associated with information storage and retrieval of a device coupled to an input/output memory management unit (IOMMU); may configure one or more registers of the memory controller with a range of addresses associated; may determine performance data based at least on one or more of an average number of transactions completed, an average number of cycles utilized by the transactions, and an average number of credits in a flow control between the memory controller and a first memory medium coupled to the memory controller; may determine that the performance data does not comply with the QoS configuration information; and if the performance data indicates that the information storage and retrieval of the device is congested, may remap the IOMMU to point to DMA buffers of a second memory medium.
1. An information handling system, comprising:
at least one processor;
a memory controller;
a memory management unit (MMU);
an input/output memory management unit (IOMMU) configured to be coupled to a device; and
a plurality of memory media coupled to the memory controller and coupled to the IOMMU;
wherein the memory controller is configured to:
receive quality of service (QoS) configuration information associated with information storage and retrieval of the device;
configure one or more registers of the memory controller with a range of addresses associated with a process or a virtual machine;
determine one or more of an average number of transactions completed in a period of time transpiring, an average number of cycles utilized by the transactions in the address range, and an average number of credits in a flow control between the memory controller and a first memory medium of the plurality of memory media;
obtain a direct memory access (DMA) address range associated with the device;
determine performance data based at least on the one or more of the average number of transactions completed in the period of time transpiring, the average number of cycles utilized by the transactions in the address range, and the average number of credits in the flow control between the memory controller and the first memory medium;
determine that the performance data does not comply with the QoS configuration information;
determine if the performance data indicates that the information storage and retrieval of the device is congested;
when the performance data indicates that the information storage and retrieval of the device is congested:
remap the IOMMU to point to DMA buffers of a second memory medium of the plurality of memory media, different from the first memory medium; and
remap the MMU to point to the DMA buffers of the second memory medium; and
when the performance data does not indicate that the information storage and retrieval of the device is congested:
remap the IOMMU to point to DMA buffers of a third memory medium of the plurality of memory media, different from the first memory medium and different from the second memory medium; and
remap the MMU to point to the DMA buffers of the third memory medium.
2. The information handling system of claim 1 , wherein a latency associated with the second memory medium is less than a latency associated with the first memory medium and is less than a latency associated with the third memory medium.
3. The information handling system of claim 1 , wherein a data throughput associated with the second memory medium is greater than a data throughput associated with the first memory medium and greater than a data throughput associated with the third memory medium.
4. The information handling system of claim 1 , wherein a latency associated with the third memory medium is greater than a latency associated with the first memory medium.
5. The information handling system of claim 1 , wherein the first memory medium includes storage class memory.
6. The information handling system of claim 1 , wherein the device includes at least one of a graphics processing unit (GPU), a peripheral component interconnect express (PCIe) device, a small computer system interface (SCSI) device, a serial attached SCSI (SAS) device, a universal serial bus (USB) device, a storage device, a fabric bus, a network interface, a host bus adapter, a device coupled to a docking station, the docking station, an Institute of Electrical and Electronics Engineers (IEEE) 1394 device, a serial advanced technology attachment (SATA) device, and an image acquisition device.
7. A method, comprising:
receiving quality of service (QoS) configuration information associated with information storage and retrieval of a device coupled to an input/output memory management unit (IOMMU) of an information handling system;
configuring a memory controller of the information handling system with a range of addresses associated with a process or a virtual machine;
configuring the memory controller to determine one or more of an average number of transactions completed in a period of time transpiring, an average number of cycles utilized by the transactions in the address range, and an average number of credits in a flow control between the memory controller and a first memory medium;
obtaining a direct memory access (DMA) address range associated with the device;
determining performance data based at least on the one or more of the average number of transactions completed in the period of time transpiring, the average number of cycles utilized by the transactions in the address range, and the average number of credits in the flow control between the memory controller and the first memory medium;
determining that the performance data does not comply with the QoS configuration information;
determining if the performance data indicates that the information storage and retrieval of the device is congested;
when the performance data indicates that the information storage and retrieval of the device is congested:
remapping the IOMMU to point to DMA buffers of a second memory medium, different from the first memory medium; and
remapping a memory management unit (MMU) of the information handling system to point to the DMA buffers of the second memory medium; and
when the performance data does not indicate that the information storage and retrieval of the device is congested:
remapping the IOMMU to point to DMA buffers of a third memory medium, different from the first memory medium and different from the second memory medium; and
remapping the MMU to point to the DMA buffers of the third memory medium.
8. The method of claim 7 , wherein a latency associated with the second memory medium is less than a latency associated with the first memory medium and is less than a latency associated with the third memory medium.
9. The method of claim 7 , wherein a data throughput associated with the second memory medium is greater than a data throughput associated with the first memory medium and greater than a data throughput associated with the third memory medium.
10. The method of claim 7 , wherein a latency associated with the third memory medium is greater than a latency associated with the first memory medium.
11. The method of claim 7 , wherein the first memory medium includes storage class memory.
12. The method of claim 7 , wherein the device includes at least one of a graphics processing unit (GPU), a peripheral component interconnect express (PCIe) device, a small computer system interface (SCSI) device, a serial attached SCSI (SAS) device, a universal serial bus (USB) device, a storage device, a fabric bus, a network interface, a host bus adapter, a device coupled to a docking station, the docking station, an Institute of Electrical and Electronics Engineers (IEEE) 1394 device, a serial advanced technology attachment (SATA) device, and an image acquisition device.
13. An memory controller, configured to:
receive quality of service (QoS) configuration information associated with information storage and retrieval of a device coupled to an input/output memory management unit (IOMMU) of an information handling system;
configure one or more registers of the memory controller with a range of addresses associated with a process or a virtual machine;
determine one or more of an average number of transactions completed in a period of time transpiring, an average number of cycles utilized by the transactions in the address range, and an average number of credits in a flow control between the memory controller and a first memory medium of a plurality of memory media coupled to the memory controller;
obtain a direct memory access (DMA) address range associated with the device;
determine performance data based at least on the one or more of the average number of transactions completed in the period of time transpiring, the average number of cycles utilized by the transactions in the address range, and the average number of credits in the flow control between the memory controller and the first memory medium;
determine that the performance data does not comply with the QoS configuration information;
determine if the performance data indicates that the information storage and retrieval of the device is congested;
when the performance data indicates that the information storage and retrieval of the device is congested:
remap the IOMMU to point to DMA buffers of a second memory medium of the plurality of memory media, different from the first memory medium; and
remap a memory management unit (MMU) of the information handling system to point to the DMA buffers of the second memory medium; and
when the performance data does not indicate that the information storage and retrieval of the device is congested:
remap the IOMMU to point to DMA buffers of a third memory medium of the plurality of memory media, different from the first memory medium and different from the second memory medium; and
remap the MMU to point to the DMA buffers of the third memory medium.
14. The memory controller of claim 13 , wherein a latency associated with the second memory medium is less than a latency associated with the first memory medium and is less than a latency associated with the third memory medium.
15. The memory controller of claim 13 , wherein a data throughput associated with the second memory medium is greater than a data throughput associated with the first memory medium and greater than a data throughput associated with the third memory medium.
16. The memory controller of claim 13 , wherein the first memory medium includes storage class memory.
17. The memory controller of claim 13 , wherein the device includes at least one of a graphics processing unit (GPU), a peripheral component interconnect express (PCIe) device, a small computer system interface (SCSI) device, a serial attached SCSI (SAS) device, a universal serial bus (USB) device, a storage device, a fabric bus, a network interface, a host bus adapter, a device coupled to a docking station, the docking station, an Institute of Electrical and Electronics Engineers (IEEE) 1394 device, a serial advanced technology attachment (SATA) device, and an image acquisition device.