IP Library Granted Patent US 10,824,524
Granted Patent B2
US 10,824,524 · App. 16/178,823 · Granted Nov 3, 2020

Systems and methods for providing continuous memory redundancy, availability, and serviceability using dynamic address space mirroring

Inventors: Krishnaprasad Koladi (Bangalore, IN); Wei G. Liu (Austin, TX); Gobind Vijayakumar (Trichy, IN); Murugan Sekar (Tindivanam, IN)
Assignee: Dell Products L.P.
G06F11/1666G06F11/1048G06F11/1484G06F11/2017G06F11/2058G06F12/0284G06F2201/815G06F2212/656G06F2212/657
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Quick Facts
Patent No.
US 10,824,524
App. No.
16/178,823
Granted
Nov 3, 2020
Kind
B2
Abstract

An information handling system may include one or more processors, a memory system communicatively coupled to the one or more processors, and a program of instructions embodied in non-transitory computer readable media and configured to, when read and executed by the one or more processors, create operating system level-mirroring of address spaces for data associated with one or more processes executing on the one or more processors and dynamically reallocate address spaces used for mirroring of the data for a process of the one or more processes from a first address space to a second address space responsive to a determination that a number of correctable bit errors of a memory page associated with the first address space exceeds a threshold.

Claims (32)

1. An information handling system comprising:

one or more processors;

a memory system communicatively coupled to the one or more processors; and

a program of instructions embodied in non-transitory computer readable media and configured to, when read and executed by the one or more processors:

receive a user selection of one or more processes tagged for mirroring;

in response to the user selection, create operating system-level mirroring of address spaces for data associated with the one or more processes executing on the one or more processors; and

dynamically reallocate address spaces used for mirroring of the data for a process of the one or more processes from a first address space to a second address space responsive to a determination that a number of correctable bit errors of a memory page associated with the first address space exceeds a threshold.

2. The information handling system of claim 1 , wherein creating operating system-level mirroring of address spaces for data associated with one or more processes executing on the one or more processors comprises, for each process of the one or more processes, selecting an address space within a non-uniform memory access (NUMA) memory domain of a processor of the one or more processors executing such process.

3. The information handling system of claim 1 , wherein dynamically reallocating an address space used for mirroring of data for the process of the one or more processes comprises selecting the second address space based on proximity of the second address space to a processor of the one or more processors executing the process.

4. The information handling system of claim 1 , wherein dynamically reallocating an address space used for mirroring of data for the process of the one or more processes comprises:

identifying a plurality of candidate address spaces for the second address space; and

selecting the second address space from the plurality of candidate address spaces based on a respective number of correctable bit errors that have occurred within each of the plurality of candidate address spaces.

5. A method comprising, in an information handling system comprising one or more processors and a memory system communicatively coupled to the one or more processors:

receiving a user selection of one or more processes tagged for mirroring;

in response to the user selection, creating operating system-level mirroring of address spaces for data associated with one or more processes executing on the one or more processors; and

dynamically reallocating address spaces used for mirroring of the data for a process of the one or more processes from a first address space to a second address space responsive to a determination that a number of correctable bit errors of a memory page associated with the first address space exceeds a threshold.

6. The method of claim 5 , wherein creating operating system-level mirroring of address spaces for data associated with one or more processes executing on the one or more processors comprises, for each process of the one or more processes, selecting an address space within a non-uniform memory access (NUMA) memory domain of a processor of the one or more processors executing such process.

7. The method of claim 5 , wherein dynamically reallocating an address space used for mirroring of data for the process of the one or more processes comprises selecting the second address space based on proximity of the second address space to a processor of the one or more processors executing the process.

8. The method of claim 5 , wherein dynamically reallocating an address space used for mirroring of data for the process of the one or more processes comprises:

identifying a plurality of candidate address spaces for the second address space; and

selecting the second address space from the plurality of candidate address spaces based on a respective number of correctable bit errors that have occurred within each of the plurality of candidate address spaces.

9. An article of manufacture comprising:

a non-transitory computer-readable medium; and

computer-executable instructions carried on the computer-readable medium, the instructions readable by a processor, the instructions, when read and executed, for causing the processor to, in an information handling system comprising one or more processors and a memory system communicatively coupled to the one or more processors:

receive a user selection of one or more processes tagged for mirroring;

in response to the user selection, create operating system-level mirroring of address spaces for data associated with one or more processes executing on the one or more processors; and

dynamically reallocate address spaces used for mirroring of the data for a process of the one or more processes from a first address space to a second address space responsive to a determination that a number of correctable bit errors of a memory page associated with the first address space exceeds a threshold.

10. The article of claim 9 , wherein creating operating system-level mirroring of address spaces for data associated with one or more processes executing on the one or more processors comprises, for each process of the one or more processes, selecting an address space within a non-uniform memory access (NUMA) memory domain of a processor of the one or more processors executing such process.

11. The article of claim 9 , wherein dynamically reallocating an address space used for mirroring of data for the process of the one or more processes comprises selecting the second address space based on proximity of the second address space to a processor of the one or more processors executing the process.

12. The article of claim 9 , wherein dynamically reallocating an address space used for mirroring of data for the process of the one or more processes comprises:

identifying a plurality of candidate address spaces for the second address space; and

selecting the second address space from the plurality of candidate address spaces based on a respective number of correctable bit errors that have occurred within each of the plurality of candidate address spaces.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2018
From: KOLADI, KRISHNAPRASAD; LIU, WEI G.; VIJAYAKUMAR, GOBIND; SEKAR, MURUGAN
To: DELL PRODUCTS L.P.
Reel/Frame 047392/0209 →
Continuity (1)
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