IP Library Granted Patent US 10,846,020
Granted Patent B2
US 10,846,020 · App. 16/179,595 · Granted Nov 24, 2020

Drive assisted storage controller system and method

Inventors: Gary B. Kotzur (Austin, TX); Marcelo Silva Saraiva (Austin, TX); William Emmett Lynn (Round Rock, TX)
Assignee: Dell Products L.P.
G06F3/0659G06F3/0604G06F3/0656G06F3/0688G06F13/1668G06F13/28G06F13/4282G06F2213/0026G06F2213/28
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Quick Facts
Patent No.
US 10,846,020
App. No.
16/179,595
Granted
Nov 24, 2020
Kind
B2
Abstract

A drive assisted storage controller system includes a first storage device that is coupled to a bus that includes a data path and a control path. The first storage device receives via the control path from a storage controller, a first peer-to-peer write command that identifies a host memory address included in a memory system, a first storage location provided in the first storage device, and a second storage location provided in a second storage device coupled to the bus. The first storage device retrieves, via the data path from the host memory address, first write data such that the first write data is not provided through the storage controller. The first storage device provides, via the control path to the second storage device, a second peer-to-peer write command that includes the second storage location. The second peer-to-peer write command causes the second storage device to retrieve the first write data from the first storage device via the data path.

Claims (72)

1. A drive assisted storage controller system, comprising:

a bus that includes a data path and a control path;

a processing system that is coupled to the data path and the control path included in the bus;

a memory system that is coupled to the processing system; and

a storage system that includes:

a storage controller that is coupled to the control path included in the bus; and

a plurality of storage devices that are each coupled to the data path and the control path included in the bus, wherein a first storage device that is included in the plurality of storage devices is configured to:

receive, via the control path from the storage controller, a first peer-to-peer write command that identifies a host memory address included in the memory system, a first storage location provided in the first storage device, and a second storage location provided in a second storage device that is included in the plurality of storage devices;

retrieve, via the data path from the host memory address included in the memory system, first write data, wherein the first write data is not provided through the storage controller; and

provide, via the control path to the second storage device, a second peer-to-peer write command that includes the second storage location and a memory location in the first storage device at which the first write data is stored, wherein the second peer-to-peer write command causes the second storage device to retrieve the first write data from the memory location in the first storage device via the data path.

2. The system of claim 1 , wherein the storage controller is configured to:

receive, via the control path included in the bus from the processing system, a mirror write command that includes the host memory address included in the memory system;

map the mirror write command to the first storage location and the second storage location; and

provide the first peer-to-peer write command to the first storage device via the control path.

3. The system of claim 1 , wherein the first storage device is configured to:

receive, via the control path from the second storage device, a first peer-to-peer write completion response that indicates that the second peer-to-peer write command has completed; and

provide, via the control path to the storage controller, a second peer-to-peer write completion response that indicates that the first peer-to-peer write command has completed, wherein the second peer-to-peer write completion response causes the storage controller to provide, via the control path to the processing system, a mirror write completion response that indicates that a mirror write command has completed.

4. The system of claim 1 , further comprising:

a bus switch that is coupled to the processing system via a first bus link included in the bus, that is coupled to the storage controller via a second bus link included in the bus, that is coupled to the first storage device via a third bus link included in the bus, and that is coupled to the second storage device via a fourth bus link included in the bus, wherein the bus switch enables the storage controller and the plurality of storage devices to issue peer-to-peer commands.

5. The system of claim 1 , wherein the first storage device is configured to:

store the first write data in the first storage device at the first storage location.

6. The system of claim 1 , wherein the second storage device is configured to:

store the first write data in the second storage device at the second storage location.

7. The system of claim 1 , wherein the first storage device is configured to:

map a buffer memory included in the first storage device to an interconnect memory space, wherein the buffer memory provides the memory location;

store the first write data at the memory location provided in the buffer memory; and

provide the memory location in the second peer-to-peer write command, wherein the second storage device retrieves, via the data path from the memory location, the first write data using the mapped buffer memory provided in the interconnect memory space and the memory location.

8. The system of claim 1 , wherein the first storage device is configured to:

receive, via the control path from the second storage device, a third peer-to-peer command that includes a third storage location of second write data provided in the second storage device; and

retrieve, via the data path from the second storage device, second write data from the third storage location.

9. A drive assist storage device, comprising:

a first storage module;

a first processing system coupled to the first storage module; and

a first memory system that is coupled to the first processing system and that includes instructions that, when executed by the first processing system, cause the first processing system to provide a drive assist engine that is configured to:

receive, via a control path of a bus that couples the first processing system to a storage controller, a first peer-to-peer write command that identifies a host memory address included in a second memory system that is coupled to the first processing system via the bus, a first storage location provided in the first storage module, and a second storage location provided in a first storage device coupled to the bus;

retrieve, via a data path of the bus from the host memory address included in the second memory system, first write data, wherein the first write data is not provided through the storage controller; and

provide, via the control path to the first storage device, a second peer-to-peer write command that includes the second storage location and a memory location in the first memory system at which the first write data is stored after the first write data is retrieved from the second memory system, wherein the second peer-to-peer write command causes the first storage device to retrieve the first write data from the memory location via the data path.

10. The device of claim 9 , wherein the drive assist engine is configured to:

receive, via the control path from the first storage device, a first peer-to-peer write completion response that indicates that the second peer-to-peer write command has completed; and

provide, via the control path to the storage controller, a second peer-to-peer write completion response that indicates that the first peer-to-peer write command has completed, wherein the second peer-to-peer write completion response causes the storage controller to provide, via the control path to a second processing system coupled to the second memory system, a mirror write completion response that indicates that a mirror write command has completed.

11. The device of claim 9 , wherein the drive assist engine is configured to:

store the first write data in the first storage module at the first storage location.

12. The device of claim 9 , further comprising:

a buffer memory coupled to the first processing system, wherein the drive assist engine is configured to:

map a portion of the buffer memory to a memory space, wherein the buffer memory provides the memory location;

store the first write data at the memory location provided in the portion of the buffer memory; and

provide the memory location in the second peer-to-peer write command, wherein the first storage device retrieves, via the data path from the memory location, the first write data using the mapped buffer memory provided in the memory space and the memory location.

13. The device of claim 9 , wherein the drive assist engine is configured to:

receive, via the control path from the first storage device, a third peer-to-peer command that includes a third storage location of second write data provided in the first storage device; and

retrieve, via the data path from the first storage device, second write data from the third storage location.

14. A method of drive assisted storage, comprising:

receiving, by a first storage device coupled to a bus via a control path of the bus from a storage controller, a first peer-to-peer write command that identifies a host memory address included in a memory system included in a processing system coupled to the bus, a first storage location provided in the first storage device, and a second storage location provided in a second storage device coupled to the bus;

retrieving, by the first storage device via a data path of the bus from the host memory address included in the memory system, first write data, wherein the first write data is not provided through the storage controller; and

providing, by the first storage device via the control path to the second storage device, a second peer-to-peer write command that includes the second storage location and a memory location in the first storage device at which the first write data is stored after the first write data is retrieved from the memory system, wherein the second peer-to-peer write command causes the second storage device to retrieve the first write data from the memory location in the first storage device via the data path.

15. The method of claim 14 , further comprising:

receiving, by the storage controller via the control path from a processing system coupled to the bus, a mirror write command that includes the host memory address included in the memory system;

mapping, by the storage controller, the mirror write command to the first storage location and the second storage location; and

providing, by the storage controller via the control path to the first storage device, the first peer-to-peer write command.

16. The method of claim 14 , further comprising:

receiving, by the first storage device via the control path from the second storage device, a first peer-to-peer write completion response that indicates that the second peer-to-peer write command has completed; and

providing, by the first storage device via the control path to the storage controller, a second peer-to-peer write completion response that indicates that the first peer-to-peer write command has completed, wherein the second peer-to-peer write completion response causes the storage controller to provide, via the control path to the processing system, a mirror write completion response that indicates that a mirror write command has completed.

17. The method of claim 14 , further comprising:

storing, by the first storage device, the first write data in the first storage device at the first storage location.

18. The method of claim 14 , further comprising:

storing, by the second storage device, the first write data in the second storage device at the second storage location.

19. The method of claim 14 , further comprising:

mapping, by the first storage device, a buffer memory included in the first storage device to an interconnect memory space, wherein the buffer memory provides the memory location;

storing, by the first storage device, the first write data at the memory location provided in the buffer memory; and

providing, by the first storage device, the memory location in the second peer-to-peer write command, wherein the second storage device retrieves, via the data path from the memory location, the first write data using the mapped buffer memory provided in the interconnect memory space and the memory location.

20. The method of claim 14 , further comprising:

receiving, by the first storage device via the control path from the second storage device, a third peer-to-peer command that includes a third storage location of second write data provided in the second storage device; and

retrieving, by the first storage device via the data path from the second storage device, second write data from the third storage location.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2018
From: KOTZUR, GARY B.; SARAIVA, MARCELO SILVA; LYNN, WILLIAM EMMETT
To: DELL PRODUCTS L.P.
Reel/Frame 047398/0969 →
Cited By (1)
US 12,326,817