Reducing variable-length pre-key to fix-length key

1. An apparatus, comprising:

at least one processor embodied in at least one computer and configured with instructions to:

receive a first pre-key, the first pre-key having a first size;

reduce the first size by at least a first logical operation using first bits of the first pre-key with second bits of the first pre-key to render a first key for decrypting at least one content, the first key having a second size smaller than the first size;

decrypt the content using the first key;

receive a second pre-key having a third size different from the first size;

reduce the third size by a logical operation using first bits of the second pre-key with second bits of the second pre-key to render a second key for decrypting the content, the second key having a size smaller than the third size; and

decrypt the content using the second key;

wherein the first pre-key comprises first bytes and second bytes, and reducing the first size comprises:

performing a logical exclusive OR operation of the first bytes across some of the bytes of the first pre-key, and not using any of the second bytes to form the first key.

2. The apparatus of claim 1 , wherein at least the first logical operation comprises an exclusive-OR operation.

3. The apparatus of claim 1 , wherein the instructions are executable to:

receive information identifying the first bits; and

use the information to execute the logical operation.

4. The apparatus of claim 1 , wherein the instructions are executable to:

receive information identifying the first size; and

use the information to execute the first logical operation.

5. The apparatus of claim 1 , wherein some or all of the bits of the first and second pre-key are the result of public key or hash operations, and the first and second keys are used with a symmetric block cipher.

6. The apparatus of claim 1 , wherein the processor is embodied in one of: a television, a set-top box, a tablet, a cell-phone.

7. The apparatus of claim 1 , wherein at least one byte of the first pre-key is not used to generate any byte of the first key.

8. The apparatus of claim 1 , wherein the instructions are executable to:

transmit information identifying the first size of the first pre-key to the receiver.

9. The apparatus of claim 1 , wherein the instructions are executable to:

transmit information identifying an offset indicating a location in the first pre-key at which to combine the first bits.

10. The apparatus of claim 1 , wherein the processor is embodied in a computer network server.

11. A method comprising:

receiving a first key having a variable size;

responsive to the variable size of the first key being greater than a second key size, reducing the variable size of the first key to a second size less than the variable size to form a reduced key whose value is a function of some but not all bytes of the first key and decrypting received content according to the reduced key;

wherein the first key comprises first bytes and second bytes, and reducing the variable size comprises:

performing a logical exclusive OR operation of the first bytes across some of the bytes of the first key, and not using any of the second bytes to form the reduced key.

12. The method of claim 11 , wherein the first key is received from Digital Rights Management (DRM) processing.

13. The method of claim 11 , wherein the first key is result of a public key or hashing cryptographic operation.

14. The method of claim 11 , comprising:

responsive to the variable size of the first key being equal to a second key size, using the first key as is and decrypting the received content according to the first key.

15. The method of claim 11 , comprising:

responsive to the variable size of the first key being smaller than a second key size, using all the bits of the first key and filling in the remaining bits up to the second key size with known values to create an expanded key, and decrypting the received content with the expanded key.

16. The method of claim 11 , comprising:

responsive to the variable size of the first key being smaller than a second key size, using all the bits of the first key and replicating bits of the first key up to the second key size to create an expanded key, and decrypting the received content according to the expanded key.

17. An assembly comprising:

at least one processor embodied in at least one computer and programmed with instructions for:

receiving a first key having a first size;

performing at least one of:

responsive to the first size of the first key being smaller than a second key size, using all the bits of the first key and filling in the remaining bits up to the second key size with known values to create an expanded key, and decrypting at least one received content with the expanded key;

responsive to the first size of the first key being smaller than a second key size, using all the bits of the first key and replicating bits of the first key up to the second key size to create an expanded key, and decrypting the received content according to the expanded key.

18. An assembly comprising:

at least one processor embodied in at least one computer and programmed with instructions for:

receiving a first key having a first size;

responsive to the first size of the first key being smaller than a second key size, using all the bits of the first key and filling in the remaining bits up to the second key size with known values to create an expanded key, and decrypting at least one received content with the expanded key.

19. An assembly comprising:

at least one processor embodied in at least one computer and programmed with instructions for:

receiving a first key having a first size;

responsive to the first size of the first key being smaller than a second key size, using all the bits of the first key and replicating bits of the first key up to the second key size to create an expanded key, and decrypting at least one received content according to the expanded key.