IP Library Granted Patent US 10,931,432
Granted Patent B2
US 10,931,432 · App. 16/184,159 · Granted Feb 23, 2021

Base station for switching between uplink periods and downlink periods in a time division manner

Inventor: Tsuyoshi Shimomura (Yokohama, JP)
Assignee: FUJITSU LIMITED
H04L5/14H04W72/0406H04W72/1236H04W88/08
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Quick Facts
Patent No.
US 10,931,432
App. No.
16/184,159
Granted
Feb 23, 2021
Kind
B2
Abstract

A base station that switches between uplink periods and downlink periods in a time division manner and performs communication, the base station includes a memory; processor circuitry coupled to the memory, wherein the processor circuitry is configured to: notify of allocation information indicating a combination of resources for time division duplex (TDD) uplink (UL) or downlink (DL) configuration at a predetermined interval; and generate control information indicating cancelation of transmission of a downlink signal, wherein the canceled transmission is configured to be performed by using one of the resources designated by the allocation information, and wherein the processor circuitry is further configured to transmit the generated control information.

Claims (29)

1. A base station that switches between uplink periods and downlink periods in a time division manner and performs communication, the base station comprising:

a memory;

processor circuitry coupled to the memory, wherein the processor circuitry is configured to:

notify of allocation information indicating a combination of resources for time division duplex (TDD) uplink (UL) or downlink (DL) configuration at a predetermined interval;

allocate a resource designated by the allocation information for transmitting first data;

when performing a latency-critical transmission using second data which has a higher delay requirement than the first data allocate a part of resources for a downlink signal designated by the allocation information to the second data;

generate control information including an instruction related to switching of the part of resources; and

transmit the generated control information.

2. The base station of claim 1 , wherein the processor circuitry is configured to notify of allocation information allocated for two or more predetermined intervals.

3. The base station of claim 2 , wherein each of the two or more predetermined intervals correspond to one of a predetermined number of subframes.

4. The base station of claim 1 , wherein the processor circuitry is further configured to:

generate change information for changing an allocation ratio of resources of uplink and downlink signals, and

transmit the generated control information including the generated change information.

5. A base station that switches between uplink periods and downlink periods in a time division manner and performs communication, the base station comprising:

a memory;

processor circuitry coupled to the memory, wherein the processor circuitry is configured to:

notify of allocation information indicating a combination of resources for time division duplex (TDD) uplink (UL) or downlink (DL) configuration at a predetermined interval;

allocate a resource designated by the allocation information for transmitting first data;

when performing a latency-critical transmission using second data which has a higher delay requirement than the first data, allocate a part of resources for a downlink signal designated by the allocation information;

generate control information for notifying that transmission of the first data using a part of resources designated by the allocation information is to be canceled; and

transmit the generated control information.

6. The base station of claim 5 , wherein the base station further comprises a receiver configured to receive first request information corresponding to the first data and second request information corresponding to the second data.

7. The base station of claim 6 , wherein resources for the first request information and the second request information are configured to be different from each other.

8. The base station of claim 5 , wherein the processor circuitry is configured to notify of the allocation information allocated for two or more predetermined intervals.

9. The base station of claim 8 , wherein each of the two or more predetermined intervals correspond to one of a predetermined number of subframes.

10. The base station of claim 6 , wherein the processor circuitry is configured to generate the control information when the receiver receives the second request information.

11. The base station of claim 5 , wherein the processor circuitry is further configured to:

generate change information for changing an allocation ratio of resources of uplink and downlink signals, and

transmit the generated change information.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2025
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 072432/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2018
From: SHIMOMURA, TSUYOSHI
To: FUJITSU LIMITED
Reel/Frame 047496/0549 →
Continuity (2)
Continuation PCTJP2016064193 · May 12, 2016
Related Publication 20190074955A1 · Mar 7, 2019