Systems and methods for support of selective processor microcode updates
An information handling system may include a plurality of processors, a basic input/output system (BIOS) comprising a program of instructions executable by one or more of the plurality of processors configured to, when executed, cause the one or more of the plurality of processors, to initialize one or more information handling resources of the information handling system, wherein the BIOS is further configured to receive a user selection of respective microcode versions desired to be loaded on each of the plurality of processors and cause each of the plurality of processors to load a respective microcode version in accordance with the user selection such that the respective microcode version loaded by a first of the plurality of processors is different than the respective microcode version loaded by a second of the plurality of processors.
1. An information handling system comprising:
a plurality of processors disposed within a single chassis of a single computer system;
a basic input/output system (BIOS) comprising a program of instructions executable by one or more of the plurality of processors configured to, when executed, cause the one or more of the plurality of processors to initialize one or more information handling resources of the information handling system, wherein the BIOS is further configured to:
receive a user selection of respective microcode versions to be loaded on each of the plurality of processors; and
cause each of the plurality of processors to load a respective microcode version in accordance with the user selection such that the respective microcode version loaded by a first of the plurality of processors is different from the respective microcode version loaded by a second of the plurality of processors, wherein the respective microcode version loaded by the first of the plurality of processors includes a security fix that decreases performance, and wherein the respective microcode version loaded by the second of the plurality of processors does not include the security fix that decreases performance.
2. The information handling system of claim 1 , wherein the BIOS is further configured to present to a user one or more options for user selection of respective microcode versions to be loaded on each of the plurality of processors.
3. The information handling system of claim 1 , wherein the user selection indicates, for each individual processor, a selection of which microcode version is to be loaded on the individual processor.
4. The information handling system of claim 1 , wherein the user selection indicates, for each individual group of a plurality of groups of the plurality of processors, which microcode version is to be loaded on processors of the individual group, wherein the processors of each individual group share at least one common characteristic.
5. The information handling system of claim 1 , wherein the BIOS is further configured to store a repository of a plurality of microcode images, each microcode image being of a different version of microcode for the plurality of processors.
6. The information handling system of claim 5 , wherein the BIOS is further configured to cause each of the plurality of processors to load its respective microcode version from the repository.
7. A method comprising:
a basic input/output system (BIOS) comprising a program of instructions executable by one or more of a plurality of processors disposed within a single chassis of a single computer system causing the one or more of the plurality of processors to:
initialize one or more information handling resources of the information handling system;
receive a user selection of respective microcode versions to be loaded on each of the plurality of processors; and
cause each of the plurality of processors to load a respective microcode version in accordance with the user selection such that the respective microcode version loaded by a first of the plurality of processors is different from the respective microcode version loaded by a second of the plurality of processors, wherein the respective microcode version loaded by the first of the plurality of processors includes a security fix that decreases performance, and wherein the respective microcode version loaded by the second of the plurality of processors does not include the security fix that decreases performance.
8. The method of claim 7 , wherein the plurality of processors are a plurality of processor cores.
9. The method of claim 7 , wherein the user selection indicates, for each individual processor, a selection of which microcode version is to be loaded on the individual processor.
10. The method of claim 7 , wherein the user selection indicates, for each individual group of a plurality of groups of the plurality of processors, which microcode version is to be loaded on processors of the individual group, wherein the processors of each individual group share at least one common characteristic.
11. The method of claim 7 , further comprising the BIOS storing a repository of a plurality of microcode images, each microcode image being of a different version of microcode for the plurality of processors.
12. The method of claim 11 , further comprising the BIOS causing each of the plurality of processors to load its respective microcode version from the repository.
13. An article of manufacture comprising:
a non-transitory computer readable medium; and
computer-executable instructions carried on the computer readable medium, the instructions executable by one or more of a plurality of processors that are disposed within a single chassis of a single computer system to cause a basic input/output system (BIOS) of the information handling system to:
initialize one or more information handling resources of the information handling system;
receive a user selection of respective microcode versions to be loaded on each of the plurality of processors; and
cause each of the plurality of processors to load a respective microcode version in accordance with the user selection such that the respective microcode version loaded by a first of the plurality of processors is different from the respective microcode version loaded by a second of the plurality of processors, wherein the respective microcode version loaded by the first of the plurality of processors includes a security fix that decreases performance, and wherein the respective microcode version loaded by the second of the plurality of processors does not include the security fix that decreases performance.
14. The article of claim 13 , the instructions for further causing the BIOS to present to a user one or more options for user selection of respective microcode versions to be loaded on each of the plurality of processors.
15. The article of claim 13 , wherein the user selection indicates, for each individual processor, a selection of which microcode version is to be loaded on the individual processor.
16. The article of claim 13 , wherein the user selection indicates, for each individual group of a plurality of groups of the plurality of processors, which microcode version is to be loaded on processors of the individual group, wherein the processors of each individual group share at least one common characteristic.
17. The article of claim 13 , the instructions for further causing the BIOS to store a repository of a plurality of microcode images, each microcode image being of a different version of microcode for the plurality of processors.
18. The article of claim 17 , the instructions for further causing the BIOS to cause each of the plurality of processors to load its respective microcode version from the repository.