Logarithmic scale analog to digital converter for wide dynamic range avalanche photodiode current companding

1. An electronic circuit comprising an analog-to-digital converter (ADC) circuit, the ADC circuit including:

a pre-amplifying transistor including a base, an emitter and a collector, the pre-amplifying transistor configured to:

receive an input voltage at the base; and

produce an output voltage at the collector according to a comparison of a reference voltage and a difference between the input voltage and a voltage at the emitter; and

a quantizer circuit operatively coupled to the emitter of the pre-amplifying transistor and configured to generate a digital value for the input voltage using the output voltage produced by the pre-amplifying transistor.

2. The electronic circuit of claim 1 , including:

an avalanche photodiode (APD); and

a diode-connected transistor operatively coupled to the APD and configured to receive current produced by the APD and generate the input voltage received at the base of the pre-amplifying transistor, wherein the input voltage varies logarithmically with the current produced by the APD.

3. The electronic circuit of claim 1 , wherein the quantizer circuit includes a successive approximation register (SAR) converter circuit.

4. The electronic circuit of claim 3 ,

wherein the SAR converter circuit includes a digital-to-analog converter (DAC) circuit including a DAC output operatively coupled to the emitter of the pre-amplifying transistor; and

wherein the pre-amplifying circuit is configured to produce the output voltage using a difference between the input voltage and a DAC output voltage.

5. The electronic circuit of claim 4 , including:

a resistive circuit element coupled to the emitter of the pre-amplifying transistor and an output of the DAC circuit; and

a voltage shifter circuit coupled to the base of the pre-amplifying transistor.

6. The electronic circuit of claim 4 , including a proportional to absolute temperature (PTAT) voltage reference coupled to an input of the DAC circuit.

7. The electronic circuit of claim 3 , wherein the SAR circuit is an 8-bit SAR circuit.

8. The electronic circuit of claim 1 , including:

an avalanche photodiode (APD); and

a first current mirror circuit operatively coupled to the APD, wherein the first current mirror circuit includes a diode-connected transistor configured to provide the input voltage to the pre-amplifying transistor.

9. The electronic circuit of claim 8 , including:

a resistive circuit element coupled to the emitter of the pre-amplifying transistor;

a voltage shifter circuit coupled to the base of the pre-amplifying transistor; and

a second current mirror coupled to the voltage shifter circuit and the first current mirror.

10. The electronic circuit of claim 9 , wherein the first current mirror circuit includes a Wilson current mirror circuit.

11. A method of operating a current monitoring circuit, the method comprising:

applying a logarithmically varying input voltage to a base of a pre-amplifying transistor;

applying an output voltage from a digital-to-analog converter (DAC) circuit to an emitter of the pre-amplifying transistor;

applying a reference current source to a collector of the pre-amplifying transistor to establish a threshold voltage and to pull a collector voltage at the collector to a high supply voltage, wherein the collector voltage is pulled down to a low supply voltage when a difference between the logarithmically varying input voltage and the output voltage from the DAC circuit is greater than the established threshold voltage; and

generating a digital value for the logarithmically varying input voltage using the collector voltage as an input to a quantizer circuit that includes the DAC circuit.

12. The method of claim 11 , including:

generating a current using an avalanche photodiode (APD); and

converting the current to the input voltage applied to the base of the pre-amplifying transistor, wherein the input voltage varies logarithmically with the current.

13. The method of claim 12 ,

wherein generating the current includes generating an APD current that varies over four decades of a logarithmic current scale; and

wherein generating the digital value includes generating digital values that are logarithmically compressed digital values of the APD current.

14. An optical receiver circuit comprising:

an avalanche photodiode (APD);

an APD current monitoring circuit including:

a converter circuit configured to convert an APD current received from the APD to an input voltage that varies logarithmically with the APD current; and

a pre-amplifying transistor including a base, an emitter and a collector, the pre-amplifying transistor configured to:

receive the input voltage at the base; and

produce an output voltage at the collector according to a comparison of a reference voltage and a difference between the input voltage and a voltage at the emitter; and

a quantizer circuit operatively coupled to the pre-amplifying transistor and configured to generate a digital value for the APD current using the output voltage produced by the pre-amplifying transistor.

15. The optical receiver circuit of claim 14 , wherein the converter circuit includes a diode-connected transistor.

16. The optical receiver circuit of claim 14 , wherein the quantizer circuit includes a successive approximation register (SAR) converter circuit.

17. The optical receiver circuit of claim 16 , wherein the SAR converter circuit includes:

a comparator circuit coupled to the collector of the pre-amplifying transistor; and

a digital to analog converter (DAC) circuit including a DAC output coupled to the emitter of the pre-amplifying transistor.

18. The optical receiver circuit of claim 17 , including:

a resistive circuit element coupled to the emitter of the pre-amplifying transistor and the output of the DAC circuit; and

a voltage shifter circuit coupled to the base of the pre-amplifying transistor and an input of the comparator.

19. The optical receiver circuit of claim 17 , including a proportional to absolute temperature (PTAT) voltage reference coupled to an input of the DAC circuit.

20. The optical receiver circuit of claim 14 , wherein the quantizer circuit is configured to generate an 8-bit digital value representing the APD current, wherein the APD varies over four decades of a logarithmic scale.

21. The optical receiver circuit of claim 14 , wherein the converter circuit includes:

a current mirror circuit operatively coupled to the APD, wherein the current mirror circuit includes a first current mirror transistor including a collector to receive the APD current and a base coupled to a second current mirror transistor, wherein the second current mirror transistor is diode-connected and provides the input voltage to the pre-amplifying transistor.