Systems and methods for performing instructions to convert to 16-bit floating-point format
Disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
1. A processor comprising:
fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a first source vector comprising N plurality of single-precision elements, and a destination vector comprising at least N plurality of 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector;
decode circuitry to decode the fetched single instruction; and
the execution circuitry to respond to the decoded single instruction as specified by the opcode.
2. The processor of claim 1 , wherein:
the single instruction is further to specify a location of a second source vector comprising N plurality of single-precision elements;
the specified destination vector comprises 2 times N 16-bit floating-point elements, first and second halves of which correspond to the first and second source vectors, respectively; and
the opcode to indicate the execution circuitry is to convert each of the elements of the specified first and second source vectors to the 16-bit floating-point format, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector.
3. The processor of claim 1 , wherein the locations of each of the specified source and destination vectors are either in registers or in memory.
4. The processor of claim 1 , wherein N is specified by the single instruction and has a value of one of 4, 8, 16, or 32.
5. The processor of claim 1 , wherein when the execution circuitry performs rounding, it does so according to a Nearest Even rounding rule.
6. The processor of claim 1 , wherein the execution circuitry is to generate all N elements of the specified destination vector in parallel.
7. A method executed by a processor, the method comprising:
fetching, using fetch circuitry, a single instruction having fields to specify an opcode and locations of a first source vector comprising N plurality of single-precision elements, and a destination vector comprising at least N plurality of 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector;
decoding, using decode circuitry, the fetched single instruction; and
responding, using the execution circuitry, to the decoded single instruction as specified by the opcode.
8. The method of claim 7 , wherein:
the single instruction is further to specify a location of a second source vector comprising N plurality of single-precision elements;
the specified destination vector comprises 2 times N 16-bit floating-point elements, first and second halves of which correspond to the first and second source vectors, respectively; and
the opcode to indicate the execution circuitry is to convert each of the elements of the specified first and second source vectors to the 16-bit floating-point format, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector.
9. The method of claim 7 , wherein the locations of each of the specified source and destination vectors are either in registers or in memory.
10. The method of claim 7 , wherein N is specified by the single instruction and has a value of one of 4, 8, 16, or 32.
11. The method of claim 7 , wherein when the execution circuitry performs rounding, it does so according to a Nearest Even rounding rule.
12. The method of claim 7 , wherein the execution circuitry is to generate all N elements of the specified destination vector in parallel.
13. A non-transitory machine-readable medium containing code that, when executed by a processor, causes the processor to perform a method comprising:
fetching, using fetch circuitry, a single instruction having fields to specify an opcode and locations of a first source vector comprising N plurality of single-precision elements, and a destination vector comprising at least N plurality of 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to a 16-bit floating-point format of a sign bit, an 8-bit exponent, and a mantissa comprising 7 explicit bits and an eighth implicit bit, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector;
decoding, using decode circuitry, the fetched single instruction; and
responding, using the execution circuitry, to the decoded single instruction as specified by the opcode.
14. The non-transitory machine-readable medium of claim 13 , wherein:
the single instruction is further to specify a location of a second source vector comprising N plurality of single-precision elements;
the specified destination vector comprises 2 times N 16-bit floating-point elements, first and second halves of which correspond to the first and second source vectors, respectively; and
the opcode to indicate the execution circuitry is to convert each of the elements of the specified first and second source vectors to 16-bit floating-point format, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector.
15. The non-transitory machine-readable medium of claim 13 , wherein the locations of each of the specified source and destination vectors are either in registers or in memory.
16. The non-transitory machine-readable medium of claim 13 , wherein when the execution circuitry performs rounding, it does so according to a Nearest Even rounding rule.