Automatic gain control for passive optical network
An automatic gain control circuit controls a gain of a burst mode amplifier. A peak detector includes an input coupled to an output of the amplifier. A plurality of resistors is coupled in series between an input of the first amplifier and the output of the first amplifier for setting the gain of the amplifier. A first gain stage is responsive to an output signal of the peak detector for disabling a first resistor of the plurality of resistors to alter the gain of the first amplifier. A second gain stage is responsive to the output signal of the peak detector for disabling a second resistor of the plurality of resistors to alter the gain of the first amplifier. A comparator responsive to the output signal of the peak detector causes a pulse generator to enable the first gain stage and second gain stage each burst mode.
1. An automatic gain control circuit for controlling a gain of an amplifier, comprising:
a peak detector including an input coupled to an output of the amplifier;
a first comparator including a first input coupled to an output of the peak detector and a second input coupled for receiving a first reference voltage;
a first conduction path including a first switching circuit with a control input of the first switching circuit coupled to an output of the first comparator, wherein a first terminal of the first conduction path is coupled to the output of the amplifier; and
a first resistor including a first terminal coupled to an input of the amplifier and a second terminal coupled to a second terminal of the first conduction path.
2. The automatic gain control circuit of claim 1 , wherein the first switching circuit includes:
a latch including a data input coupled to the output of the first comparator; and
a transistor including a first conduction terminal coupled to the second terminal of the first resistor, a second conduction terminal coupled to the output of the amplifier, and a control input coupled to an output of the latch.
3. The automatic gain control circuit of claim 2 , further including:
a second comparator including a first input coupled to the output of the peak detector and a second input coupled for receiving a second reference voltage; and
a pulse generator including an input coupled to an output of the second comparator and an output coupled to an enable input of the latch.
4. The automatic gain control circuit of claim 1 , further including:
a second comparator including a first input coupled to the output of the peak detector and a second input coupled for receiving a second reference voltage;
a second conduction path including a second switching circuit with a control input of the second switching circuit coupled to an output of the second comparator, wherein a first terminal of the second conduction path is coupled to the output of the amplifier; and
a second resistor including a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to a second terminal of the second conduction path.
5. The automatic gain control circuit of claim 4 , further including:
a third comparator including a first input coupled to the output of the peak detector and a second input coupled for receiving a third reference voltage;
a third conduction path including a third switching circuit with a control input of the third switching circuit coupled to an output of the third comparator, wherein a first terminal of the third conduction path is coupled to the output of the amplifier; and
a third resistor including a first terminal coupled to the second terminal of the second resistor and a second terminal coupled to a second terminal of the third conduction path.
6. The automatic gain control circuit of claim 5 , further including a fourth resistor coupled between the second terminal of the third resistor and the output of the amplifier.
7. An automatic gain control circuit for controlling a gain of a first amplifier, comprising:
a peak detector including an input coupled to an output of the first amplifier;
a plurality of resistors coupled in series between an input of the first amplifier and the output of the first amplifier for setting the gain of the first amplifier;
a first gain stage responsive to an output signal of the peak detector for disabling a first resistor of the plurality of resistors to alter the gain of the first amplifier, wherein the first gain stage includes,
(a)a first comparator including a first input coupled to an output of the peak detector and a second input coupled for receiving a first reference voltage,
(b) a first conduction path including a first switching circuit with a control input of the first switching circuit coupled to an output of the first comparator, wherein a first terminal of the first conduction path is coupled to the output of the amplifier, and
(c) the first resistor of the plurality of resistors including a first terminal coupled to an input of the amplifier and a second terminal coupled to a second terminal of the first conduction path; and
a second gain stage responsive to the output signal of the peak detector for disabling a second resistor of the plurality of resistors to alter the gain of the first amplifier.
8. The automatic gain control circuit of claim 7 , wherein the first switching circuit includes:
a latch including a data input coupled to the output of the first comparator; and
a transistor including a first conduction terminal coupled to the first resistor, a second conduction terminal coupled to the output of the first amplifier, and a control input coupled to an output of the latch.
9. The automatic gain control circuit of claim 8 , wherein the latch includes a reset input coupled for receiving a reset signal.
10. The automatic gain control circuit of claim 8 , further including:
a second comparator including a first input coupled to the output of the peak detector and a second input coupled for receiving a second reference voltage; and
a pulse generator including an input coupled to an output of the second comparator and an output coupled to an enable input of the latch.
11. The automatic gain control circuit of claim 7 , wherein the second gain stage includes:
a second comparator including a first input coupled to the output of the peak detector and a second input coupled for receiving a reference voltage; and
a second conduction path including a second switching circuit with a control input of the second switching circuit coupled to an output of the second comparator, wherein the second conduction path disables the second resistor.
12. The automatic gain control circuit of claim 7 , further including:
a second amplifier; and
a resistor divider network coupled between an output of the second amplifier and a power supply terminal for generating a plurality of reference voltages.
13. A method of making an automatic gain control circuit for controlling a gain of a first amplifier, comprising:
providing a peak detector including an input coupled to an output of the first amplifier;
providing a plurality of resistors coupled in series between an input of the first amplifier and the output of the first amplifier for setting the gain of the first amplifier;
providing a first gain stage responsive to an output signal of the peak detector for disabling a first resistor of the plurality of resistors to alter the gain of the first amplifier, wherein the first gain stage includes,
(a)a first comparator including a first input coupled to an output of the peak detector and a second input coupled for receiving a first reference voltage,
(b) a first conduction path including a first switching circuit with a control input of the first switching circuit coupled to an output of the first comparator, wherein a first terminal of the first conduction path is coupled to the output of the amplifier, and
(c) the first resistor of the plurality of resistors including a first terminal coupled to an input of the amplifier and a second terminal coupled to a second terminal of the first conduction path; and
providing a second gain stage responsive to the output signal of the peak detector for disabling a second resistor of the plurality of resistors to alter the gain of the first amplifier.
14. The method of claim 13 , wherein providing the first switching circuit includes:
providing a latch including a data input coupled to the output of the first comparator; and
providing a transistor including a first conduction terminal coupled to the first resistor, a second conduction terminal coupled to the output of the first amplifier, and a control input coupled to an output of the latch.
15. The method of claim 14 , wherein the latch includes a reset input coupled for receiving a reset signal.
16. The method of claim 14 , further including:
providing a second comparator including a first input coupled to the output of the peak detector and a second input coupled for receiving a second reference voltage; and
providing a pulse generator including an input coupled to an output of the second comparator and an output coupled to an enable input of the latch.
17. The method of claim 13 , wherein the second gain stage includes:
providing a second comparator including a first input coupled to the output of the peak detector and a second input coupled for receiving a reference voltage; and
providing a second conduction path including a second switching circuit with a control input of the second switching circuit coupled to an output of the second comparator, wherein the second conduction path disables the second resistor.
18. The method of claim 13 , further including:
providing a second amplifier; and
providing a resistor divider network coupled between an output of the second amplifier and a power supply terminal for generating a plurality of reference voltages.
19. The method of claim 17 , wherein the second switching circuit includes:
a latch including a data input coupled to the output of the second comparator; and
a transistor including a first conduction terminal coupled to the second resistor, a second conduction terminal coupled to the output of the first amplifier, and a control input coupled to an output of the latch.
20. The automatic gain control circuit of claim 11 , wherein the second switching circuit includes:
a latch including a data input coupled to the output of the second comparator; and
a transistor including a first conduction terminal coupled to the second resistor, a second conduction terminal coupled to the output of the first amplifier, and a control input coupled to an output of the latch.