Method for producing an association list

1. A method for determining signal values from a field programmable gate array (FPGA) at runtime of the FPGA, the method comprising:

creating an allocation map based on an FPGA source code;

processing, by the FPGA source code, at least a first signal at a first location;

mapping at least one first register to the first signal;

listing, in the allocation map, the first signal and the first register as being mapped to one another;

processing, a second signal at a second location in the FPGA source code, wherein it is automatically detected that a value of the second signal at a second location in the FPGA source code is determined from the value of the first signal in accordance with a first calculation rule;

listing, in the allocation map, the second signal, the first register, and the calculation rule as mapped to one another;

implementing the FPGA source code on the FPGA;

reading out a first value of the first signal at runtime of the FPGA from the first register; and

determining a second value of the second signal from the first value using the first calculation rule.

2. The method according to claim 1 , wherein the first signal and the second signal are identical and the calculation rule is the identity.

3. The method according to claim 1 , wherein the second signal includes a subset of the bits of the first signal and an allocation rule defines the bits of the first signal, which determine the value of the second signal.

4. The method according to claim 1 , wherein the second signal is connected with the first signal only by one or more bit-preserving arithmetic operations.

5. The method according to claim 1 , wherein the second signal is connected with the first signal by one or more bit-changing arithmetic operations.

6. The method according to claim 5 , wherein the bit-changing arithmetic operation outputs the calculation result at the same clock rate.

7. The method according to claim 5 , wherein the bit-changing arithmetic operation is a combinational logic operation.

8. The method according to claim 5 , wherein the bit-changing arithmetic operation offsets the first signal against a third signal,

wherein a third register is mapped to the third signal,

wherein, in the allocation map, the third register is additionally mapped to the first signal, and

wherein a first calculation rule indicates how the value of the second signal is calculated from the value of the first signal and the value of the third signal.

9. The method according to claim 1 , wherein a second register is mapped to the second signal in the FPGA source code, and

wherein, in the allocation map, in addition to the first register and the calculation rule, the second register is listed as mapped to the second signal.

10. The method according to claim 9 , wherein the duration of the readout of the second register and the duration of calculating the second signal value from the first signal value is estimated from the first signal value, and based on the estimates, the faster method is specified as a method in the allocation map.

11. The method according to claim 1 , wherein a second register is mapped to the second signal in the FPGA source code,

wherein in the allocation map, in addition to the first register and the calculation rule, the second register is mapped to the second signal, and

wherein a decision is automatically made at runtime whether the second signal value is read out of the second register or the second signal value is determined from the first signal value using the calculation rule.