Systems and methods for reducing standby power in floating body memory devices
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
1. A semiconductor memory array configured for reducing standby power, said array comprising:
a plurality of floating body memory cells configured to store charge representative of data; and
at least two floating body cells serially connected to form a reference cell;
wherein current conducted through said at least one of said plurality of floating body memory cells is reduced to a fraction of said current when passing through said reference cell.
2. The array of claim 1 , wherein said at least two floating body cells of said reference cell are set to state 1.
3. The array of claim 1 , wherein said reference cell is used for at least one of: a current reference, a voltage reference or a monitor of transient response to bit line discharge.
4. A semiconductor memory array configured for reducing standby power, said array comprising:
a plurality of floating body memory cells configured to store charge representative of data; and
at least two more of said floating body memory cells interconnected by a segmented source line to form a reference cell.
5. The array of claim 4 , comprising:
a plurality of said reference cells connected in a dedicated column or row of said array and to different rows or columns of said floating body memory cells configured to store charge representative of data; and
a dedicated reference bit line connected to said plurality of reference cells.
6. The array of claim 4 , comprising:
a plurality of said reference cells connected to different rows or columns of said floating body memory cells configured to store charge representative of data; and
source isolation devices connected between said reference cells.
7. The array of claim 1 , further comprising source isolation devices configured to set said reference cell to state 1.
8. The array of claim 7 , wherein said source isolation devices are off during normal operation.
9. The array of claim 7 , wherein said source isolation devices are configured to be activated to set said reference cell to state 1.
10. The array of claim 4 , further comprising source isolation devices configured to set said reference cell to state 1.
11. The array of claim 10 , wherein said source isolation devices are off during normal operation.
12. The array of claim 10 , wherein said source isolation devices are configured to be activated to set said reference cell to state 1.