Semiconductor device with phase difference detection circuit between a clock and strobe signal

1. A semiconductor device comprising:

a phase difference detection circuit comprising:

a clock signal input and a strobe signal input,

a first delay circuit operatively coupled to the clock signal input;

a frequency divider circuit operatively coupled to the strobe signal input;

a second delay circuit operatively coupled to the frequency divider circuit; and

a detection signal generation circuit operatively coupled to both the first delay circuit and the second delay circuit;

wherein:

a clock signal received at the clock signal input is delayed by the first delay circuit by a first predetermined amount of time to thereby generate a delayed clock signal;

a strobe signal input to the frequency divider circuit has a frequency, and is divided to thereby provide a divided strobe signal having a lower frequency than the frequency of the received strobe signal and which is provided to the second delay circuit;

the second delay circuit delays the divided strobe signal by a second predetermined amount of time to thereby provide a write clock signal from the frequency-divided strobe signal,

the detection signal generation circuit receives the delayed clock signal circuit from the first delay circuit and receives the write clock signal from the second delay circuit and generates therefrom a detection signal by, detecting a phase difference between the clock signal and the strobe signal, the detection signal being generated in synchronization with the clock; and

a control signal generation circuit, which receives the write clock signal and the detection signal and which is configured to: store the detection signal, in synchronization with the write clock, and output the stored detection signal as a control signal, which is provided to a phase adjustment circuit;

wherein the strobe signal is a signal which toggles only during a preset period, and

wherein a frequency of the strobe signal is set to 2N times the frequency of the clock, wherein N is a positive integer.

2. The semiconductor device according to claim 1 , wherein the clock and the strobe signal are signals which have different frequencies.

3. The semiconductor device according to claim 1 , wherein the second delay circuit provides substantially the same delay as the first delay circuit.

4. The semiconductor device according to claim 1 , wherein the control signal generation circuit comprises:

a second latch signal generation circuit configured to output the detection signal as a second latch signal in synchronization with the write clock; and

a second buffer circuit configured to buffer the second latch signal, in response to a pulse of the write clock, and configured to generate the control signal.

5. The semiconductor device according to claim 1 , wherein the detection signal is generated at the logic level of the strobe signal at a rising edge time of the clock.

6. The semiconductor device according to claim 1 , wherein detection signal is stored in synchronization with a rising edge of the write clock.

7. A semiconductor device comprising:

a write leveling control circuit, the write leveling control circuit comprising:

a clock signal input and a strobe signal input,

a first delay circuit operatively coupled to the clock signal input;

a frequency divider circuit operatively coupled to the strobe signal input;

a second delay circuit operatively coupled to the frequency divider circuit; and

a detection signal generation circuit operatively coupled to both the first delay circuit and the second delay circuit;

wherein:

a clock signal received at the clock signal input is delayed by the first delay circuit by a first predetermined amount of time to thereby generate a delayed clock signal;

a strobe signal input to the frequency divider circuit has a frequency, and is divided to thereby provide a divided strobe signal having a lower frequency than the frequency of the received strobe signal and which is provided to the second delay circuit;

the second delay circuit delays the divided strobe signal by a second predetermined amount of time to thereby provide a write clock signal from the frequency-divided strobe signal,

the detection signal generation circuit receives the delayed clock signal circuit from the first delay circuit and receives the write clock signal from the second delay circuit and generates therefrom a detection signal by detecting a phase difference between the delayed clock signal and the write clock signal, the detection signal being generated in synchronization with the clock; and

a control signal generation circuit, which receives the write clock signal and the detection signal and which is configured to: store the detection signal, in synchronization with the write clock, and output the stored detection signal as a control signal, which is provided to a phase adjustment circuit;

wherein a frequency of the strobe signal is set to 2N times the frequency of the clock, wherein N is a positive integer.

8. The semiconductor device according to claim 7 , wherein the detection signal is enabled when a phase of the strobe signal is earlier than a phase of the clock.

9. The semiconductor device according to claim 7 , wherein the clock and the strobe signal are signals which have different frequencies.

10. The semiconductor device according to claim 7 , wherein a frequency of the divided strobe signal is set to 1/2N times the frequency of the strobe signal, wherein N represents a positive integer.

11. The semiconductor device according to claim 7 , wherein the second delay circuit is set to have the same delay amount as the first delay circuit.

12. The semiconductor device according to claim 7 , wherein the detection signal generation circuit comprises:

a first latch signal generation circuit configured to output the write clock as a first latch signal in synchronization with the delayed clock; and

a first buffer circuit configured to buffer the first latch signal and generate the detection signal.

13. The semiconductor device according to claim 7 , wherein the control signal generation circuit comprises:

a second latch signal generation circuit configured to output the detection signal as a second latch signal in synchronization with the write clock; and

a second buffer circuit configured to buffer the second latch signal, in response to a pulse of the write clock, and generate the control signal.

14. The semiconductor device according to claim 7 , wherein the detection signal is generated at the logic level of the strobe signal at a rising edge time of the clock.