IP Library Granted Patent US 10,958,507
Granted Patent B2
US 10,958,507 · App. 16/195,359 · Granted Mar 23, 2021

Web handling system

Inventors: Md M. Haque (Oklahoma City, OK); Darcy Winter (Oklahoma City, OK); Wolfram Ploetz (Oklahoma City, OK); Darren Irons (Oklahoma City, OK); Shomari Head (Oklahoma City, OK); Rainer Sokoll (Oklahoma City, OK)
Assignee: Maxcess Americas, Inc.
H04L41/0672B65H23/02B65H23/04H04L12/422H04L12/437H04L41/0816H04L45/28H04L47/13B65H2301/4148B65H2557/12
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Quick Facts
Patent No.
US 10,958,507
App. No.
16/195,359
Granted
Mar 23, 2021
Kind
B2
Abstract

A web handling system is described, including a plurality of web handling controllers and a web handling process logic controller networked to form a ring network. A processor of the web handling process logic controller being configured to determine whether a fault exists within the ring network, and responsive to determining that a fault exists within the ring network, to generate and send signals throughout the ring network to switch the configuration of the ring network to at least one linear network.

Claims (11)

1. A web handling system comprising:

a plurality of web handling controllers, each of the web handling controllers having a web handling processor, a first communication port and a second communication port; and

a web handling process logic controller having a processor, a third communication port and a fourth communication port, the first communication port, the second communication port, the third communication port and the fourth communication port being connected to form a ring network, the processor of the web handling process logic controller being always configured as an active ring supervisor to determine whether a fault exists within the ring network, and responsive to determining that a fault exists within the ring network, to generate and send signals throughout the ring network to switch the configuration of the ring network to at least one linear network and

wherein at least one of the web handling processor or the processor of the web handling process logic controller synchronizes a slave clock to a master clock using a series of timestamped synchronization packets to determine an offset between the master clock and the slave clock, in which a first departure time of a first timestamped synchronization packet is denoted t1, and a first receive time of the first timestamped synchronization packet is denoted t2, a second departure time of a second timestamped synchronization packet is denoted t3, and a second receive time of the second timestamped synchronization packet is denoted t4, and wherein a network propagation delay+offset=t2−t1; and the network propagation time−Offset=t4−t3.

2. The web handling system of claim 1 , wherein one of the web handling controllers is a component of a web guiding system.

3. The web handling system of claim 1 , wherein one of the web handling controllers is a component of a web tension control system.

4. The web handling system of claim 1 , wherein one of the web handling controllers is a component of a video web inspection system.

5. An apparatus, comprising:

a web handling process logic controller having a processor, a first communication port and a second communication port, the processor configured to control the first communication port, and the second communication port to be a part of a ring network, the processor of the web handling process logic controller also being always configured as an active ring supervisor to determine whether a fault exists within the ring network, and responsive to determining that a fault exists within the ring network, to generate and send first signals via the first communication port and second signals via the second communication port, the first and second signals including instructions to switch the configuration of the ring network to at least one linear network, wherein the processor synchronizes a slave clock to a master clock using a series of timestamped synchronization packets to determine an offset between the master clock and the slave clock, in which a first departure time of a first timestamped synchronization packet is denoted t1, and a first receive time of the first timestamped synchronization packet is denoted t2, a second departure time of a second timestamped synchronization packet is denoted t3, and a second receive time of the second timestamped synchronization packet is denoted t4, and wherein a network propagation delay+offset=t2−t1; and the network propagation time−Offset=t4−t3.

6. The apparatus of claim 5 , wherein the processor is configured to be a ring supervisor that monitors traffic on the first and second communication ports, the processor also controlling the traffic on the first and second communication ports to selectively prevent packets from circulating within the ring network.

7. The apparatus of claim 6 , wherein the processor is configured to be the only ring supervisor within the ring network.

Assignments (3)
MERGER Recorded Sep 12, 2025
From: FIFE CORPORATION
To: MAXCESS AMERICAS, INC.
Reel/Frame 072240/0248 →
MERGER Recorded Sep 12, 2025
From: MAXCESS AMERICAS, INC.
To: MAXCESS INTERNATIONAL CORPORATION
Reel/Frame 072240/0331 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2018
From: HAQUE, MD M.; WINTER, DARCY J.; PLOETZ, WOLFRAM; IRONS, DARREN S.; HEAD, SHOMARI; SOKOLL, RAINER
To: FIFE CORPORATION
Reel/Frame 047547/0218 →
Continuity (3)
Division 15667280 · Aug 2, 2017
Provisional Application 62369982 · Aug 2, 2016
Related Publication 20190089580A1 · Mar 21, 2019