Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD

1. A chassis front-end, comprising:

a switchboard including an Ethernet switch, a processor, a Baseboard Management Controller (BMC), and a mid-plane connector to connect to a mid-plane; and

a mid-plane including at least one storage device connector to connect to at least one storage device and a speed logic to inform the at least one storage device of a speed of the Ethernet switch, wherein the Ethernet switch is one of a first Ethernet switch supporting a first Ethernet speed and a second Ethernet switch supporting a second Ethernet speed.

2. The chassis front-end according to claim 1 , wherein the at least one storage device includes at least one Solid State Drive (SSD).

3. The chassis front-end according to claim 2 , wherein the speed logic includes a Complex Programmable Logic Device (CPLD) that communicates with the at least one SSD using the at least one storage device connector.

4. The chassis front-end according to claim 3 , wherein the CPLD uses at least one speed pin on the at least-one storage device connector to inform the at least one SSD of the speed of the Ethernet switch.

5. The chassis front-end according to claim 3 , wherein the CPLD uses at least one General Purpose Input/Output (GPIO) pin on the at least-one storage device connector to inform the at least one SSD of the speed of the Ethernet switch, the at least one GPIO pin latched after informing the at least one SSD of the speed of the Ethernet switch.

6. The chassis front-end according to claim 2 , wherein:

the speed of the Ethernet switch may be written into a Vital Product Data (VPD) of an Electrically Erasable Programmable Read-Only Memory (EEPROM); and

the at least one SSD may read the speed of the Ethernet switch from the VPD of the EEPROM.

7. The chassis front-end according to claim 2 , wherein the mid-plane further includes a wireless transmitter to transmit the speed of the Ethernet switch to the at least one SSD.

8. The chassis front-end according to claim 2 , wherein the speed of the Ethernet switch may be written to a register in a Field Programmable Gate Array (FPGA) of the at least one SSD via the at least one storage device connector.

9. The chassis front-end according to claim 2 , further comprising a second switchboard, the second switchboard including a second Ethernet switch, a second processor, a second BMC, and a second mid-plane connector to connect to the mid-plane,

wherein the at least one SSD is a dual port SSD and communicates with both the switchboard and the second switchboard via the at least one storage device connector and the mid-plane.

10. A method, comprising:

receiving an Ethernet speed of an Ethernet switch at a Baseboard Management Controller (BMC) on a switchboard from a chassis; and

informing, by the BMC, a storage device in the chassis connected to a chassis front-end of the Ethernet speed of the Ethernet switch, the chassis front-end including the switchboard and a mid-plane, wherein the Ethernet switch is one of a first Ethernet switch supporting a first Ethernet speed and a second Ethernet switch supporting a second Ethernet speed.

11. The method according to claim 10 , wherein informing, by the BMC, the storage device in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch includes informing, by the BMC, a Solid State Drive (SSD) in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch.

12. The method according to claim 11 , wherein informing, by the BMC, the Solid State Drive (SSD) in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch includes:

informing a Complex Programmable Logic Device (CPLD) by the BMC of the Ethernet speed of the Ethernet switch; and

informing, by the CPLD, the SSD in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch.

13. The method according to claim 12 , wherein informing, by the CPLD, the SSD in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch includes using at least one speed pin on a storage device connector connecting the SSD to the chassis front-end.

14. The method according to claim 12 , wherein informing, by the CPLD, the SSD in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch includes:

using at least one General Purpose Input/Output (GPIO) pin on a storage device connector connecting the SSD to the chassis front-end; and

latching the at least one GPIO pin latched after informing the SSD of the speed of the Ethernet switch.

15. The method according to claim 11 , wherein informing, by the BMC, the storage device in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch includes writing, by the BMC, the Ethernet speed of the Ethernet switch to a Vital Product Data (VPD) of an Electrically Erasable Programmable Read-Only Memory (EEPROM), wherein the SSD may read the Ethernet speed of the Ethernet switch from the VPD of the EEPROM.

16. The method according to claim 11 , wherein informing, by the BMC, the storage device in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch includes wirelessly transmitting the Ethernet speed of the Ethernet switch from the BMC to the SSD.

17. The method according to claim 11 , wherein informing, by the BMC, the storage device in the chassis connected to the chassis front-end of the Ethernet speed of the Ethernet switch includes writing, by the BMC, the Ethernet speed of the Ethernet switch to a register in a Field Programmable Gate Array (FPGA) of the SSD using a storage device connector.

18. The method according to claim 11 , wherein:

the chassis front-end includes a second switchboard connected to the mid-plane; and

the SSD is a dual port SSD and communicates with both the switchboard and the second switchboard via a storage device connector and the mid-plane.

19. A storage device, comprising:

data storage to store data;

a controller to manage reading and writing data to the data storage;

a storage device connector to connect the storage device to a mid-plane in a chassis, the storage device connector including a plurality of pins;

a bit file storage to store at least two Ethernet speed bit files; and

a mapping logic to map the data from the data storage to the plurality of pins on the storage device connector responsive to one of the at least two Ethernet speed bit files.

20. The storage device according to claim 19 , wherein the storage device is a Solid State Drive (SSD).