Phased array antenna panel having reduced passive loss of received signals
A phased array antenna panel includes a first plurality of antennas, a first radio frequency (RF) front end chip, a second plurality of antennas, a second RF front end chip, and a combiner RF chip. The first and second RE front end chips receive respective first and second input signals from the first and second pluralities of antennas, and produce respective first and second output signals based on the respective first and second input signals. The combiner RF chip can receive the first and second output signals and produce a power combined output signal that is a combination of powers of the first and second output signals. Alternatively, a power combiner can receive the first and second output signals and produce a power combined output signal, and the combiner RF chip can receive the power combined output signal.
1. A phased array antenna panel, comprising:
a first radio frequency (RF) front end chip between a first plurality of antennas,
wherein said first RF front end chip is configured to:
receive first input signals from said first plurality of antennas, and
produce a first phase-shifted output signal based on a first phase shift of said first input signals;
a second RF front end chip between a second plurality of antennas,
wherein said second RF front end chip is configured to:
receive second input signals from said second plurality of antennas, and
produce a second phase-shifted output signal based on a second phase shift of said second input signals; and
a combiner RF chip configured to:
receive said first phase-shifted output signal and said second phase-shifted output signal,
combine a first power of said first phase-shifted output signal and a second power of said second phase-shifted output signal, and
produce a power combined output signal based on said combination of said first power signal and said second power signal.
2. The phased array antenna panel of claim 1 , wherein said combiner RF chip comprises a lumped-element power combiner.
3. The phased array antenna panel of claim 2 , wherein said lumped-element power combiner comprises at least one of an on-chip capacitor or an inductor.
4. The phased array antenna panel of claim 1 , wherein said first phase-shifted output signal and said second phase-shifted output signal are fed into respective input buffers in said combiner RF chip.
5. The phased array antenna panel of claim 1 , wherein said combiner RF chip includes an output buffer, and
wherein said output buffer is configured to generate a buffered power combined output signal based on said power combined output signal.
6. The phased array antenna panel of claim 1 , wherein said combiner RF chip is substantially centered between said first RF front end chip and said second RF front end chip.
7. The phased array antenna panel of claim 1 , further comprising a master chip, wherein said master chip is configured to:
provide a first phase shift signal to said first plurality of antennas via said first RF front end chip, and
provide a second phase shift signal to said second plurality of antennas via said second RF front end chip.
8. The phased array antenna panel of claim 1 , further comprising a master chip, wherein said master chip is further configured to:
provide a first amplitude control signal to said first plurality of antennas via said first RF front end chip, and
provide a second amplitude control signal to said second plurality of antennas via said second RF front end chip.
9. A phased array antenna panel, comprising:
a first radio frequency (RF) front end chip between a first plurality of antennas,
wherein said first RF front end chip is configured to:
receive first input signals from said first plurality of antennas, and
produce a first phase-shifted output signal based on a first phase shift of said first input signals;
a second RF front end chip between a second plurality of antennas,
wherein said second RF front end chip is configured to:
receive second input signals from said second plurality of antennas, and
produce a second phase-shifted output signal based on a second phase shift of said second input signals;
a power combiner on a substrate of said phased array antenna panel,
wherein said power combiner comprises microstrips, and wherein said microstrips are configured to:
receive said first phase-shifted output signal and said second phase-shifted output signal, and
output a power combined output signal based on said first phase-shifted output signal and said second phase-shifted output signal; and
a combiner RF chip configured to receive said power combined output signal.
10. The phased array antenna panel of claim 9 , wherein said combiner RF chip is further configured to produce a buffered power combined output signal based on said power combined output signal.
11. The phased array antenna panel of claim 9 , wherein said power combined output signal is fed into an input buffer in said combiner RF chip.
12. The phased array antenna panel of claim 9 , wherein each antenna of said first plurality of antennas and said second plurality of antennas comprises vertically polarized probe and horizontally polarized probe.
13. The phased array antenna panel of claim 9 , wherein said combiner RF chip is substantially centered between said first RF front end chip and said second RF front end chip.
14. The phased array antenna panel of claim 9 , further comprising a master chip, wherein said master chip is configured to:
provide a first phase shift signal to said first plurality of antennas via said first RF front end chip, and
provide a second phase shift signal to said second plurality of antennas via said second RF front end chip.
15. The phased array antenna panel of claim 9 , further comprising a master chip, wherein said master chip is further configured to:
provide a first amplitude control signal to said first plurality of antennas via said first RF front end chip, and
provide a second amplitude control signal to said second plurality of antennas via said second RF front end chip.
16. A phased array antenna panel, comprising:
a first radio frequency (RF) front end chip between a first plurality of antennas,
wherein said first RF front end chip is configured to:
receive first input signals from said first plurality of antennas, and
produce a first amplified output signal based on a first amplification of said first input signals;
a second RF front end chip between a second plurality of antennas,
wherein said second RF front end chip is configured to:
receive second input signals from said second plurality of antennas, and
produce a second amplified output signal based on a second amplification of said second input signals; and
a combiner RF chip configured to:
receive said first amplified output signal and said second amplified output signal,
combine a first power of said first amplified output signal and a second power of said second amplified output signal, and
produce a power combined output signal based on said combination of said first power signal and said second power signal.