Analog computer architecture for fast function optimization
An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.
1. An analog circuit for solving optimization algorithms, the analog circuit comprising:
a plurality of voltage controlled current sources;
a plurality of capacitors, operatively coupled in parallel to the plurality of voltage controlled current sources, respectively;
a first inductor, operatively coupled in series between a first pair of the plurality of capacitors and the plurality of voltage controlled current sources and a second pair of the plurality of capacitors and the plurality of voltage controlled current sources; and
a second inductor, operatively coupled in series between the second pair of the plurality of capacitors and the plurality of voltage controlled current sources and a third pair of the plurality of capacitors and the plurality of voltage controlled current sources, wherein the analog circuit is to solve the optimization algorithms with multi-variable cost functions, and wherein the multi-variable cost functions are convex, and wherein the analog circuit is to increase a probability of solving for a global minimum.
2. The analog circuit of claim 1 , wherein the analog circuit is to solve the optimization algorithms in less than 500 nanoseconds.
3. An analog circuit for solving optimization algorithms, the analog circuit comprising:
a plurality of voltage controlled current sources;
a plurality of capacitors, operatively coupled in parallel to the plurality of voltage controlled current sources, respectively;
a first inductor, operatively coupled in series between a first pair of the plurality of capacitors and the plurality of voltage controlled current sources and a second pair of the plurality of capacitors and the plurality of voltage controlled current sources; and
a second inductor, operatively coupled in series between the second pair of the plurality of capacitors and the plurality of voltage controlled current sources and a third pair of the plurality of capacitors and the plurality of voltage controlled current sources, wherein the analog circuit is to solve the optimization algorithms as part of a model-predictive control scheme.
4. The analog circuit of claim 3 , wherein the analog circuit is to solve the optimization algorithms in less than 500 milliseconds.
5. The analog circuit of claim 3 , wherein the analog circuit is implemented by a field programmable analog array (FPAA).
6. The analog circuit of claim 5 , wherein the FPAA is configured digitally.
7. A field programmable analog array (FPAA) for solving optimization algorithms, configured to comprise:
a plurality of voltage controlled current sources;
a plurality of capacitors, each capacitor operatively coupled in parallel to one of the plurality of voltage controlled current sources, respectively, to form a plurality of voltage controlled current source and capacitor pairs; and
a plurality of energy-storage components, each energy-storage component of the plurality of energy-storage components operatively coupled in series between the plurality of voltage controlled current source and capacitor pairs, wherein the plurality of energy-storage components is a plurality of operational amplifiers.
8. The FPAA of claim 7 , wherein the plurality of energy-storage components is a plurality of capacitors.
9. The FPAA of claim 7 , wherein the FPAA is to solve the optimization algorithms in less than 500 milliseconds.
10. The FPAA of claim 9 , wherein the FPAA is to solve the optimization algorithms in less than 500 nanoseconds.
11. The FPAA of claim 7 , wherein the FPAA is to solve distributed optimization algorithms.
12. The FPAA of claim 7 , wherein the FPAA is to solve the optimization algorithms with multi-variable cost functions.
13. The FPAA of claim 12 , wherein the FPAA is to increase a probability of solving for a global minimum when the multi-variable cost functions are convex.
14. The FPAA of claim 7 , wherein the FPAA is configured digitally.
15. A method comprising:
receiving an optimization problem to be solved; and
generating, by a processing device, a digital program for a field programmable analog array (FPAA) to increase a probability of solving for a global minimum when the multi-variable cost functions are convex, wherein an output of the digital program is to digitally configure the FPAA to execute the optimization problem in an analog manner, wherein the digital program controls a plurality of energy-storage components, each energy-storage component of the plurality of energy-storage components operatively coupled in series between a plurality of voltage controlled current source and capacitor pairs.
16. The method of claim 15 , wherein the FPAA is to solve the optimization problem in less than 500 nanoseconds.
17. The method of claim 15 , wherein the FPAA is configured digitally.
18. The method of claim 15 , wherein the plurality of energy-storage components is at least one of a plurality of capacitors or a plurality of operational amplifiers.