Parallel fault simulator with back propagation enhancement
This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.
1. A method comprising:
injecting, by a computing system, a fault at a first node of a simulated integrated circuit design having been input with a stimulus vector, wherein alarm logic is configured to trigger indicating a detection of the injected fault;
identifying, by the computing system, which intermediate nodes of the simulated integrated circuit, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger; and
generating, by the computing system, a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic was triggered.
2. The method of claim 1 , further comprising propagating, by the computing system, the fault values associated with the injected fault through the intermediate nodes, wherein the propagated fault values trigger the alarm logic indicating the detection of the injected fault.
3. The method of claim 2 , wherein the identifying of which of the intermediate nodes have fault values that prompt the alarm logic to trigger is performed in response to the detection of the injected fault.
4. The method of claim 2 , further comprising recording a diagnostic coverage event based on the detection of the injected fault at the first node of the simulated integrated circuit design, wherein the fault coverage presentation includes the recorded diagnostic coverage event.
5. The method of claim 1 , wherein the identifying of which of the intermediate nodes have fault values that prompt the alarm logic to trigger further comprises performing back-propagation analysis by traversing the intermediate nodes from the alarm logic towards the first node.
6. The method of claim 5 , wherein the back-propagation analysis is performed on a clock cycle-by-clock cycle basis.
7. The method of claim 1 , further comprising recording a diagnostic coverage event for each of the intermediate nodes identified to have the fault values that prompt the alarm logic to trigger, wherein the fault coverage presentation includes the recorded diagnostic coverage event.
8. An apparatus comprising at least one non-transitory computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
injecting a fault at a first node of a simulated integrated circuit design having been input with a stimulus vector, wherein alarm logic is configured to trigger indicating a detection of the injected fault;
identifying which intermediate nodes of the simulated integrated circuit, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger; and
generating a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic was triggered.
9. The apparatus of claim 8 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising propagating the fault values associated with the injected fault through the intermediate nodes, wherein the propagated fault values trigger the alarm logic indicating the detection of the injected fault.
10. The apparatus of claim 9 , wherein the identifying of which of the intermediate nodes have fault values that prompt the alarm logic to trigger is performed in response to the detection of the injected fault.
11. The apparatus of claim 9 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising recording a diagnostic coverage event based on the detection of the injected fault at the first node of the simulated integrated circuit design, wherein the fault coverage presentation includes the recorded diagnostic coverage event.
12. The apparatus of claim 8 , wherein the identifying of which of the intermediate nodes have the fault values that prompt the alarm logic to trigger further comprises performing back-propagation analysis by traversing the intermediate nodes from the alarm logic towards the first node.
13. The apparatus of claim 12 , wherein the back-propagation analysis is performed on a clock cycle-by-clock cycle basis.
14. The apparatus of claim 8 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising recording a diagnostic coverage event for each of the intermediate nodes identified to have fault values that prompt the alarm logic to trigger, wherein the fault coverage presentation includes the recorded diagnostic coverage event.
15. A system comprising:
a memory system configured to store computer-executable instructions; and
a computing system, in response to execution of the computer-executable instructions, is configured to:
inject a fault at a first node of a simulated integrated circuit design having been input with a stimulus vector, wherein alarm logic is configured to trigger indicating a detection of the injected fault,
identify which intermediate nodes of the simulated integrated circuit, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger, and
generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic was triggered.
16. The system of claim 15 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to propagate the fault values associated with the injected fault through the intermediate nodes, wherein the propagated fault values trigger the alarm logic indicating the detection of the injected fault.
17. The system of claim 16 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to identify which of the intermediate nodes have fault values that prompt the alarm logic to trigger in response to the detection of the injected fault.
18. The system of claim 16 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to record a diagnostic coverage event based on the detection of the injected fault at the first node of the simulated integrated circuit design, wherein the fault coverage presentation includes the recorded diagnostic coverage event.
19. The system of claim 15 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to identify of which of the intermediate nodes have fault values that prompt the alarm logic to trigger by performing back-propagation analysis which traverses the intermediate nodes from the alarm logic towards the first node.
20. The system of claim 15 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to record a diagnostic coverage event for each of the intermediate nodes identified to have the fault values that prompt the alarm logic to trigger, wherein the fault coverage presentation includes the recorded diagnostic coverage event.