Read time-out managers and memory systems including the read time-out managers
A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.
1. A read time-out manager comprising:
a counter configured to generate a counter output signal based on a first cycle time; and
a plurality of timers each configured to be assigned a read identification to measure a time-out period corresponding to the read identification,
wherein each of the plurality of timers operates in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.
2. The read time-out manager of claim 1 , wherein when each of the time-out periods is set to be a period corresponding to 2 m cycle times of a clock signal (where, “m” denotes a natural number), the counter and each of the timers are respectively configured to have “a” bits and “b” bits (where, a sum of the value of “a” and the value of “b” is equal to the value of “m”).
3. The read time-out manager of claim 2 , wherein the first cycle time is set to be a period corresponding to 2 a cycle times of the clock signal, and the second cycle time is set to be a period corresponding to 2 (a+b) cycle times of the clock signal.
4. The read time-out manager of claim 2 , wherein a countable capacity of the counter is set to be equal to a countable capacity of each of the plurality of timers.
5. The read time-out manager of claim 2 , wherein a countable capacity of the counter is set to be different from a countable capacity of each of the plurality of timers.
6. The read time-out manager of claim 1 , wherein the counter includes:
a multiplexer configured to firstly output initial data inputted to a first input terminal of the multiplexer as output data in response to a reset signal and configured to, thereafter, output data inputted to a second input terminal of the multiplexer as the output data;
a register configured to receive and output the output data of the multiplexer in synchronization with a clock signal;
an adder configured to perform an addition operation for output data of the register to generate added data and configured to output the added data to the second input terminal of the multiplexer; and
a comparator configured to compare the output data of the register with reference data and configured to generate the counter output signal according to the comparison result.
7. The read time-out manager of claim 6 , wherein the register is realized using D-flipflops.
8. The read time-out manager of claim 1 , wherein each of the plurality of timers includes:
a multiplexer configured to firstly output initial data inputted to a first input terminal of the multiplexer as output data in response to an initialization control signal and configured to, thereafter, output data inputted to a second input terminal of the multiplexer as the output data;
a register configured to receive and output the output data of the multiplexer in synchronization with the counter output signal;
a subtracter configured to perform a subtraction operation for output data of the register to generate subtracted data and configured to output the subtracted data to the second input terminal of the multiplexer; and
a comparator configured to compare the output data of the register with reference data and configured to generate the time-out signal according to the comparison result.
9. The read time-out manager of claim 8 , wherein the initialization control signal is inputted to the multiplexer included in a timer from the plurality of timers based on a read identification inputted to the read time-out manager.
10. The read time-out manager of claim 8 , wherein the register included in each of the plurality of timers is realized using D-flipflops.
11. A memory system comprising:
a memory medium; and
a memory controller configured to control an operation for accessing the memory medium,
wherein the memory controller includes a read time-out manager configured to perform time-out operations for a plurality of read identifications of read data, the read data to be read out from the memory medium based on read commands, and
wherein the read time-out manager comprises:
a counter configured to generate a counter output signal based on a first cycle time; and
a plurality of timers each configured to be assigned a read identification from the plurality of read identifications to measure a time-out period corresponding to the read identification,
wherein each of the plurality of timers operates in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.
12. The memory system of claim 11 , wherein when each of the time-out periods is set to be a period corresponding to 2 m cycle times of a clock signal (where, “m” denotes a natural number), the counter and each of the timers are respectively configured to have “a” bits and “b” bits (where, a sum of the value of “a” and the value of “b” is equal to the value of “m”).
13. The memory system of claim 12 , wherein the first cycle time is set to be a period corresponding to 2 a cycle times of the clock signal, and the second cycle time is set to be a period corresponding to 2 (a+b) cycle times of the clock signal.
14. The memory system of claim 12 , wherein a countable capacity of the counter is set to be equal to a countable capacity of each of the plurality of timers.
15. The memory system of claim 12 , wherein a countable capacity of the counter is set to be different from a countable capacity of each of the plurality of timers.
16. The memory system of claim 11 , wherein the counter includes:
a multiplexer configured to firstly output initial data inputted to a first input terminal of the multiplexer as output data in response to a reset signal and configured to, thereafter, output data inputted to a second input terminal of the multiplexer as the output data;
a register configured to receive and output the output data of the multiplexer in synchronization with a clock signal;
an adder configured to perform an addition operation for output data of the register to generate added data and configured to output the added data to the second input terminal of the multiplexer; and
a comparator configured to compare the output data of the register with reference data and configured to generate the counter output signal according to the comparison result.
17. The memory system of claim 16 , wherein the register is realized using D-flipflops.
18. The memory system of claim 11 , wherein each of the plurality of timers includes:
a multiplexer configured to firstly output initial data inputted to a first input terminal of the multiplexer as output data in response to an initialization control signal and configured to, thereafter, output data inputted to a second input terminal of the multiplexer as the output data;
a register configured to receive and output the output data of the multiplexer in synchronization with the counter output signal;
a subtracter configured to perform a subtraction operation for output data of the register to generate subtracted data and configured to output the subtracted data to the second input terminal of the multiplexer; and
a comparator configured to compare the output data of the register with reference data and configured to generate the time-out signal according to the comparison result.
19. The memory system of claim 18 , wherein the initialization control signal is inputted to the multiplexer included in a timer from the plurality of timers based on a read identification from the plurality of read identifications inputted to the read time-out manager.
20. The memory system of claim 18 , wherein the register included in each of the plurality of timers is realized using D-flipflops.
21. The memory system of claim 11 , wherein the memory controller further includes a command and data processor configured to transmit the plurality of read identifications to the read time-out manager in response to the read commands and configured to execute an operation for terminating the time-out operation for a read identification from the plurality of read identifications in response to the time-out signal, corresponding to the read identification, outputted from the read time-out manager.