Multi-photodiode pixel cell

1. An apparatus comprising:

a semiconductor substrate comprising a light incident surface to receive light;

a first pinned photodiode;

a second pinned photodiode, the first pinned photodiode and the second pinned photodiode forming a stack structure in the semiconductor substrate along a first axis perpendicular to the light incident surface, the stack structure enabling the first pinned photodiode and the second pinned photodiode to, respectively, convert a first component of the light and a second component of the light to first charge and second charge;

a barrier layer sandwiched between the first pinned photodiode and the second pinned photodiode;

one or more capacitors formed in the semiconductor substrate and configured to:

generate a first voltage based on the first charge during a first read out period, and

generate a second voltage based on the second charge during a second read out period;

one or more control structures configured to control an electrical potential difference between a first electrical potential of the barrier layer and a second electrical potential of the semiconductor substrate in the first read out period and the second read out period, the one or more control structures comprising at least one of:

a first control structure that extends from a first surface of the semiconductor substrate into the semiconductor substrate along the first axis and has a portion adjacent to the barrier layer along a second axis perpendicular to the first axis, the first control structure being configured to conduct a first bias voltage to the barrier layer to control the first electrical potential of the barrier layer, or

a second control structure formed on and electrically connected to a second surface of the semiconductor substrate via an electrical contact, the second control structure being configured to conduct a second bias voltage to the semiconductor substrate to control the second electrical potential of the semiconductor substrate.

2. The apparatus of claim 1 , wherein each of the first pinned photodiode and the second pinned photodiode comprises:

a P-type semiconductor layer; and

an N-type region completely embedded within the P-type semiconductor layer and isolated from other components of the apparatus.

3. The apparatus of claim 1 , wherein each of the first pinned photodiode and the second pinned photodiode comprises:

an N-type semiconductor layer; and

a P-type region completely embedded within the N-type semiconductor layer and isolated from other components of the apparatus.

4. The apparatus of claim 1 ,

wherein the first pinned photodiode is configured to convert photons of light of a first wavelength range associated with infrared light to the first charge; and

wherein the second pinned photodiode is configured to convert photons of light of a second wavelength range associated with a component of visible light to the second charge.

5. The apparatus of claim 1 , wherein the first pinned photodiode and the second pinned photodiode form the stack structure such that (a) the light traverses the second pinned photodiode to reach the first pinned photodiode, or (b) the light traverses the first pinned photodiode to reach the second pinned photodiode.

6. The apparatus of claim 5 ,

wherein the first pinned photodiode and the barrier layer forms part of a controllable transmission path for transmitting the second charge from the second pinned photodiode to the one or more capacitors;

wherein the apparatus further comprises a control circuit configured to:

in the first read out period:

control, via the one or more control structures, the electrical potential difference to cause the barrier layer to:

block the second charge from the second pinned photodiode from reaching the one the one or more capacitors, and

transfer the first charge from the first pinned photodiode to the one or more capacitors to generate the first voltage;

and

in the second read out period:

control, via the one or more control structures, the electrical potential difference to cause the barrier layer to allow the second charge to flow from the second pinned photodiode, via the first pinned photodiode, to the one or more capacitors to generate the second voltage.

7. The apparatus of claim 6 , wherein the first control structure comprises one or more deep trench isolation (DTI) structures extending along the first axis within the semiconductor substrate; and

wherein the control circuit is configured to control the first electric potential at the barrier layer based on applying the first bias voltage at the one or more DTI structures to control an electric field across the barrier layer along the second axis.

8. The apparatus of claim 6 ,

wherein the control circuit is configured to control, based on applying the second bias voltage at the electrical contact, the second electric potential at a portion of the semiconductor substrate to control the electric potential difference between the barrier layer and the portion of the semiconductor substrate including the second pinned photodiode.

9. The apparatus of claim 8 , wherein the portion of the semiconductor substrate including the second pinned photodiode comprises a third surface;

wherein the semiconductor substrate further includes a fourth surface opposite to the first surface, the one or more capacitors being formed under the third surface;

wherein the apparatus further comprise a transfer gate on the third surface, the transfer gate being configured to control a flow of the first charge or of the second charge from the first pinned photodiode to the one or more capacitors.

10. The apparatus of claim 9 ,

wherein the semiconductor substrate further comprises one or more deep trench isolation (DTI) structures extending from the fourth surface along the first axis;

wherein the one or more DTI structures do not extend completely through the portion of the semiconductor substrate and do not reach the third surface;

wherein the semiconductor substrate comprises a connection region that extends along the first axis and provides an electrical connection between the electrical contact on the fourth surface and the portion of the semiconductor substrate; and

wherein the control circuit comprises a voltage source connected to the electrical contact on the fourth surface to control the second electric potential at the portion of the semiconductor substrate.

11. The apparatus of claim 9 ,

wherein the semiconductor substrate further comprises one or more deep trench isolation (DTI) structures extending from the third surface along the first axis;

wherein the third surface comprises the electrical contact; and

wherein the control circuit comprises a voltage source connected to the electrical contact on the third surface to control the second electric potential at the portion of the semiconductor substrate.

12. The apparatus of claim 11 , wherein the one or more DTI structures do not extend completely through the portion of the semiconductor substrate and do not reach the second surface;

wherein the semiconductor substrate comprises a connection region that extends along the first axis and provides an electrical connection between the electrical contact on the first surface and the portion of the semiconductor substrate; and

wherein the control circuit comprises a voltage source connected to the electrical contact on the first surface to control the second electric potential at the portion of the semiconductor substrate.

13. The apparatus of claim 12 , wherein the portion of the semiconductor substrate is a first portion;

wherein the apparatus further comprises one or more guard rings that insulate the one or more DTI structures from a second portion of the semiconductor substrate external to the first and second pinned photodiodes.

14. The apparatus of claim 9 , wherein the first surface includes the third surface or the fourth surface; and

wherein the second surface includes the third surface or the fourth surface.

15. The apparatus of claim 1 , wherein the one or more capacitors comprise one capacitor; and

wherein the apparatus is configured to reset the one capacitor between the transfer of the first charge and the transfer of the second charge.

16. The apparatus of claim 1 , wherein the one or more capacitors comprise a first capacitor and a second capacitor;

wherein the first capacitor is configured to store the first charge; and

wherein the second capacitor is configured to store the second charge.

17. The apparatus of claim 1 , wherein the first control structure comprises a conductive material and one or more isolation sidewalls that insulates the conductive material from the semiconductor substrate.

18. The apparatus of claim 1 , wherein at least one of the first surface or the second surface is the light receiving surface.

19. The apparatus of claim 1 , wherein the first surface and the second surface are the same surface.

20. The apparatus of claim 1 , wherein the first control structure comprises a conductor or a semiconductor surrounded by an insulator.

21. The apparatus of claim 1 , wherein the portion is a first portion; and

wherein the first control structure has a second portion adjacent to one of the first pinned photodiode or the second pinned photodiode.

22. A method comprising:

receiving light through a light incident surface of a semiconductor substrate;

converting, by a first pinned photodiode, a first component of the light to first charge;

converting, by a second pinned photodiode that forms a stack structure with the first pinned photodiode in the semiconductor substrate along a first axis perpendicular to the light incident surface, a second component of the light to second charge;

in a first read out period:

applying a first bias voltage at one or more control structures to set a first electrical potential difference between a first electrical potential of a barrier layer and a second electrical potential of the semiconductor substrate to block the second charge from entering the first pinned photodiode, the barrier layer being sandwiched between the first pinned photodiode and the second pinned photodiode, and

transferring the first charge to one or more capacitors formed in the semiconductor substrate to generate a first voltage; and

in a second read out period:

applying a second bias voltage at the one or more control structures to set a second electrical potential difference between the first electrical potential of the barrier layer and the second electrical potential of the semiconductor substrate to transfer the second charge from the second pinned photodiode to the second pinned photodiode, and

transferring the second charge to the one or more capacitors to generate a second voltage,

wherein the one or more control structures comprise at least one of:

a first control structure that extends from a first surface of the semiconductor substrate into the semiconductor substrate along the first axis and has a portion adjacent to the barrier layer along a second axis perpendicular to the first axis, wherein the first control structure conducts the first bias voltage and the second bias voltage to the barrier layer to set the first electrical potential at the barrier layer based on, respectively, the first bias voltage and the second bias voltage, or

a second control structure formed on and electrically connected to a second surface of the semiconductor substrate via an electrical contact, wherein the second control structure conducts the first bias voltage and the second bias voltage to the semiconductor substrate to set the second electrical potential at the semiconductor substrate based on, respectively, the first bias voltage and the second bias voltage.