IP Library Granted Patent US 10,944,270
Granted Patent B1
US 10,944,270 · App. 16/212,370 · Granted Mar 9, 2021

GaN circuit drivers for GaN circuit loads

Inventors: Daniel Marvin Kinzer (El Segundo, CA); Santosh Sharma (Rancho Santa Margarita, CA); Ju Zhang (Monterey Park, CA)
Assignee: NAVITAS SEMICONDUCTOR LIMITED
H02J7/00H01L23/49503H01L23/49562H01L23/49575H01L23/528H01L25/072H01L27/0248H01L27/088H01L27/0883H01L29/1033H01L29/2003H01L29/402H01L29/41758H02M1/088H02M3/157H02M3/1584H02M3/1588H03K3/012H03K3/356017H03K17/102H03K19/018507H01L2924/00H01L2924/0002H02M3/155H02M2001/0048Y02B40/00Y02B70/10
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Quick Facts
Patent No.
US 10,944,270
App. No.
16/212,370
Granted
Mar 9, 2021
Kind
B1
Abstract

An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Claims (26)

1. A level shift circuit comprising:

a GaN-based level shifting circuit including active and passive circuit elements formed on one or more substrates that comprise GaN, the GaN-based level shifting circuit having an input and an output, wherein in response to the input receiving an input signal referenced to a first voltage, the GaN-based level shifting circuit generates an output signal at the output, wherein the output signal is referenced to a second voltage.

2. The level shift circuit of claim 1 wherein the second voltage is at least 13 volts higher than the first voltage.

3. The level shift circuit of claim 1 wherein the second voltage is 80 to 400 volts higher than the first voltage.

4. The level shift circuit of claim 1 wherein the output signal is inverted as compared to the input signal.

5. The level shift circuit of claim 1 wherein the output signal controls a gate terminal of a high side switch, and wherein the high side switch includes a high side switch source connected to a switch node and a high side switch drain connected to a voltage source.

6. The level shift circuit of claim 5 wherein the GaN-based level shifting circuit is at least partially disposed on a first GaN die and the high side switch is disposed on a second GaN die.

7. The level shift circuit of claim 6 wherein the second GaN die includes a receiver circuit that receives the output signal, modulates the output signal and transmits a control signal to a high side switch driver circuit.

8. The level shift circuit of claim 1 comprising a GaN-based transistor that receives the input signal and generates the output signal.

9. The level shift circuit of claim 8 wherein the GaN-based transistor is an enhancement mode GaN transistor.

10. The level shift circuit of claim 8 wherein a drain of the GaN-based transistor is the output, a source of the GaN-based transistor is coupled to a ground and a gate of the GaN-based transistor is the input.

11. A method of operating a level shift circuit, the method comprising:

receiving an input signal at an input node of a GaN-based level shifting circuit wherein the input node is referenced to a first voltage and is formed on a GaN-based substrate; and

generating an output signal at an output node of the GaN-based level shifting circuit in response to receiving the input signal, wherein the output signal is referenced to a second voltage;

wherein the second voltage is different from the first voltage.

12. The method of claim 11 wherein the second voltage is at least 13 volts higher than the first voltage.

13. The method of claim 11 wherein the second voltage is 80 to 400 volts higher than the first voltage.

14. The method of claim 11 wherein the output signal is inverted as compared to the input signal.

15. The method of claim 11 wherein the output signal controls a gate terminal of a high side switch, and wherein the high side switch includes a high side switch source connected to a switch node and a high side switch drain connected to a voltage source.

16. The method of claim 15 wherein the level shift circuit is disposed on a first GaN die and the high side switch is disposed on a second GaN die.

17. The method of claim 16 wherein the second GaN die includes a receiver circuit that receives the output signal, modulates the output signal and transmits a control signal to a high side switch driver circuit.

18. The method of claim 11 comprising a GaN-based transistor that receives the input signal and generates the output signal.

19. The method of claim 18 wherein the GaN-based transistor is an enhancement mode GaN transistor.

20. The method of claim 18 wherein a drain of the GaN-based transistor is the output node, a source of the GaN-based transistor is coupled to a ground and a gate of the GaN-based transistor is the input node.

21. A level shift circuit comprising:

a GaN-based level shifting circuit including at least one GaN transistor and at least one passive circuit element that is formed on a substrate comprising GaN, the level shifting circuit having an input and an output, wherein in response to the input receiving an input signal referenced to a first voltage, the GaN-based level shifting circuit generates an output signal at the output, wherein the output signal is referenced to a second voltage.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTS AND THE RECEIVING PARTY'S POSTAL CODE PREVIOUSLY RECORDED AT REEL: 053864 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 9, 2021
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 056758/0314 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2020
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 053864/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2018
From: KINZER, DANIEL MARVIN; SHARMA, SANTOSH; ZHANG, JU
To: NAVITAS SEMICONDUCTOR, INC.
Reel/Frame 047698/0555 →
Continuity (5)
Continuation 15903398 · Feb 23, 2018
Continuation 15658242 · Jul 24, 2017
Continuation 14737259 · Jun 11, 2015
Provisional Application 62127725 · Mar 3, 2015
Provisional Application 62051160 · Sep 16, 2014
Cited By (1)
US 12,261,517