Computation of neural network node by neural network inference circuit

1. A neural network inference circuit for executing a neural network that comprises a plurality of computation nodes at a plurality of layers, each of a set of the computation nodes comprising a dot product of input values and weight values, the neural network inference circuit comprising:

a plurality of dot product core circuits, each dot product core circuit comprising:

a set of memories for storing a plurality of input values and a plurality of weight values; and

a set of adder tree circuits for computing dot products of sets of input values and sets of weight values stored in the set of memories; and

a bus that connects the plurality of dot product core circuits, the bus comprising one or more aggregation circuits,

wherein, for a particular computation node of the neural network, at least two of the dot product core circuits compute partial dot products using a set of input values and a set of weight values stored in the memories of the respective dot product core circuits and at least one of the aggregation circuits of the bus combines the partial dot products computed by the at least two dot product core circuits to compute the dot product for the particular computation node.

2. The neural network inference circuit of claim 1 , wherein:

the particular computation node is a first computation node of the neural network, the set of input values is a first set of input values and the set of weights is a first set of weights;

the at least two dot product core circuits compute partial dot products for a second computation node of the neural network using a second set of input values and a second set of weight values stored in the memories of the respective dot product core circuits; and

at least one of the aggregation circuits of the bus combines the partial dot products for the second computation node to compute the dot product for the particular computation node.

3. The neural network inference circuit of claim 2 , wherein the partial dot products for the first and second computation nodes are computed simultaneously.

4. The neural network inference circuit of claim 1 , wherein each dot product core circuit computes partial dot products for a plurality of computation nodes simultaneously.

5. The neural network inference circuit of claim 4 , wherein the plurality of computation nodes are part of a same layer of the neural network.

6. The neural network inference circuit of claim 4 , wherein the plurality of computation nodes have a same set of input values with different sets of weight values.

7. The neural network inference circuit of claim 1 , wherein:

each of the dot product core circuits further comprises a set of memory control circuits for (i) loading input values from the set of memories of the dot product core circuit into an input buffers of the dot product core circuit and (ii) loading weight values from the set of memories of the dot product core circuit into a plurality of weight buffers of the dot product core circuit; and

each different adder tree circuit of a particular dot product core circuit computes a partial dot product of a set of input values loaded into the input buffer and a different set of weight values loaded into a different weight buffer.

8. The neural network inference circuit of claim 7 , wherein the different sets of weight values are weight values for different computation nodes of the neural network.

9. The neural network inference circuit of claim 1 , wherein each of the dot product core circuits comprises a same number of adder tree circuits, each adder tree circuit having an index.

10. The neural network inference circuit of claim 9 , wherein the partial dot products for the particular computation node are computed in the at least two dot product core circuits by adder tree circuits having a same index.

11. The neural network inference circuit of claim 10 , wherein the adder tree circuits having the same index in different dot product core circuits provide their computed partial dot products to a same aggregation circuit of the bus.

12. The neural network inference circuit of claim 10 , wherein adder tree circuits having different indices provide their computed partial dot products to different aggregation circuits of the bus.

13. The neural network inference circuit of claim 1 , wherein the bus comprises a plurality of independent aggregation circuits, each different aggregation circuit corresponding to a different adder tree circuit of a particular dot product core circuit.

14. The neural network inference circuit of claim 1 , wherein the set of memories comprises a bank of random access memory (RAM), wherein a first block of the RAM bank for a particular dot product core circuit is allocated to the input values and a second block of the RAM bank for the particular dot product core circuit is allocated to the weight values.

15. The neural network inference circuit of claim 14 , wherein the RAM for the particular dot product core circuit stores (i) all of the weight values used by the particular dot product core circuit for the entire neural network and (ii) input values for up to two layers of the neural network.

16. The neural network inference circuit of claim 15 , wherein the input values for the particular computation node are overwritten by input values for subsequent nodes of the neural network.

17. The neural network inference circuit of claim 1 further comprising a set of post-processing circuits that receive aggregated dot products from the aggregation circuits.

18. The neural network inference circuit of claim 17 , wherein the particular computation node comprises (i) the dot product, (ii) a set of operations applied to the dot product, and (iii) a non-linear activation function applied to a result of the set of operations.

19. The neural network inference circuit of claim 18 , wherein each of the post-processing circuits comprises a set of circuits for the set of operations and a circuit for applying the non-linear activation function to an output of the set of circuits for the set of operations.

20. The neural network inference circuit of claim 19 , wherein the set of operations comprises an adder for applying a bias factor and a multiplier for applying a scale factor.