Memory system, control method, and control device

1. A memory system comprising:

a memory including blocks, each of the blocks including one or more sub-blocks, each of the one or more sub-blocks including nonvolatile memory cells; and

a controller electrically connected to the memory and configured to:

obtain read frequency of at least one of the sub blocks,

move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block,

obtain read frequency of at least one of the blocks including a first block,

in a case where the read frequency of the first block exceeds a first frequency, detect a data error rate of at least one of the sub-blocks in the first block,

in a case where the data error rate of the at least one of the sub-blocks in the first block exceeds a first rate, perform a movement of data stored in the at least one of the sub-blocks in the first block,

in a case where the data error rate of the at least one of the sub-blocks in the first block does not exceed the first rate, not perform the movement of data stored in the at least one of the sub-blocks in the first block,

in a case where the read frequency of a first sub-block among the at least one of the sub-blocks in the first block exceeds the first frequency, write data stored in the first sub-block into a second block by a first write method, and

in a case where the read frequency of a second sub-block among the at least one of the sub-blocks in the first block does not exceed the first frequency, write data stored in the second sub-block into a third block by a second write method, the third block being different from the second block, wherein

a number of bits of the data written into a nonvolatile memory cell in the second block is smaller than the number of bits of the data written into a nonvolatile memory cell in the third block.

2. The memory system according to claim 1 , wherein the controller is further configured to

write the data stored in the first sub-block into the second block with a first error correction coding, and

write the data stored in the second sub-block into the third block with a second error correction coding having an error correction capability not higher than an error correction capability of the first error correction coding.

3. The memory system according to claim 1 , wherein the controller is further configured to

write the data stored in the first sub-block into the second block so that a threshold voltage distribution of nonvolatile memory cells in the second block has a first variation,

write the data stored in the second sub-block into the third block so that a threshold voltage distribution of nonvolatile memory cells in the third block has a second variation, wherein

the first variation is smaller than the second variation.

4. The memory system according to claim 1 , wherein the controller is further configured to

write the data stored in the first sub-block into the second block by a first write method so that a threshold voltage distribution of nonvolatile memory cells in the second block has a first center voltage, and

write the data stored in the second sub-block into the third block by a second write method so that a threshold voltage distribution of nonvolatile memory cells in the third block has a second center voltage, wherein

the first center voltage is higher than the second center voltage.

5. The memory system according to claim 1 , wherein the controller is further configured to perform garbage collection and control the movement of data stored in the at least one of the sub-blocks by the garbage collection.

6. The memory system according to claim 1 , wherein the at least one of the sub-blocks includes at least one of

a group of the nonvolatile memory cells connected to a word line,

a group of the nonvolatile memory cells connected to word lines, or

a group of the nonvolatile memory cells storing data specified by a logical address range.

7. A memory system comprising:

a memory including blocks, each of the blocks including one or more sub-blocks, each of the one or more sub-blocks including nonvolatile memory cells; and

a controller electrically connected to the memory and configured to:

obtain read frequency of at least one of the sub-blocks,

move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block,

obtain read frequency of at least one of the blocks including a first block,

in a case where the read frequency of the first block exceeds a first frequency, detect a data error rate of at least one of the sub-blocks in the first block,

in a case where the data error rate of the at least one of the sub-blocks in the first block exceeds a first rate, perform a movement of data stored in the at least one of the sub-blocks in the first block,

in a case where the data error rate of the at least one of the sub-blocks in the first block does not exceed the first rate, not perform the movement of data stored in the at least one of the sub-blocks in the first block,

in a case where the read frequency of a first sub-block among the at least one of the sub-blocks in the first block exceeds the first frequency, write data stored in the first sub-block into a second block with a first error correction coding, and

in a case where the read frequency of a second sub-block among the at least one of the sub-blocks in the first block does not exceed the first frequency, write data stored in the second sub-block into a third block with a second error correction coding, the third block being different from the second block, the second error correction coding having an error correction capability not higher than an error correction capability of the first error correction coding.

8. The memory system according to claim 7 , wherein the controller is further configured to:

write the data stored in the first sub-block into the second block by a first write method, and

write the data stored in the second sub-block into the third block by a second write method, wherein

a number of bits of the data written into a nonvolatile memory cell in the second block is smaller than the number of bits of the data written into a nonvolatile memory cell in the third block.

9. The memory system according to claim 7 , wherein the controller is further configured to:

write the data stored in the first sub-block into the second block so that a threshold voltage distribution of nonvolatile memory cells in the second block has a first variation, and

write the data stored in the second sub-block into the third block so that a threshold voltage distribution of nonvolatile memory cells in the third block has a second variation, wherein

the first variation is smaller than the second variation.

10. The memory system according to claim 7 , wherein the controller is further configured to:

write the data stored in the first sub-block into the second block by a first write method so that a threshold voltage distribution of nonvolatile memory cells in the second block has a first center voltage, and

write the data stored in the second sub-block into the third block by a second write method so that a threshold voltage distribution of nonvolatile memory cells in the third block has a second center voltage, wherein

the first center voltage is higher than the second center voltage.

11. The memory system according to claim 7 , wherein the controller is further configured to perform garbage collection and control the movement of data stored in the at least one of the sub-blocks by the garbage collection.

12. The memory system according to claim 7 , wherein the at least one of the sub-blocks includes at least one of

a group of the nonvolatile memory cells connected to a word line,

a group of the nonvolatile memory cells connected to word lines, or

a group of the nonvolatile memory cells storing data specified by a logical address range.

13. A memory system comprising:

a memory including blocks, each of the blocks including one or more sub-blocks, each of the one or more sub-blocks including nonvolatile memory cells; and

a controller electrically connected to the memory and configured to:

obtain read frequency of at least one of the sub-blocks,

move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block,

obtain read frequency of at least one of the blocks including a first block,

in a case where the read frequency of the first block exceeds a first frequency, detect a data error rate of at least one of the sub-blocks in the first block,

in a case where the data error rate of the at least one of the sub-blocks in the first block exceeds a first rate, perform a movement of data stored in the at least one of the sub-blocks in the first block,

in a case where the data error rate of the at least one of the sub-blocks in the first block does not exceed the first rate, not perform the movement of data stored in the at least one of the sub-blocks in the first block,

in a case where the read frequency of a first sub-block among the at least one of the sub-blocks in the first block exceeds the first frequency, write data stored in the first sub-block into a second block so that a threshold voltage distribution of nonvolatile memory cells in the second block has a first variation, and

in a case where the read frequency of a second sub-block among the at least one of the sub-blocks in the first block does not exceed the first frequency, write data stored in the second sub-block into a third block so that a threshold voltage distribution of nonvolatile memory cells in the third block has a second variation, the third block being different from the second block, wherein

the first variation is smaller than the second variation.

14. The memory system according to claim 13 , wherein the controller is further configured to:

write the data stored in the first sub-block into the second block by a first write method, and

write the data stored in the second sub-block into the third block by a second write method, wherein

a number of bits of the data written into a nonvolatile memory cell in the second block is smaller than the number of bits of the data written into a nonvolatile memory cell in the third block.

15. The memory system according to claim 13 , wherein the controller is further configured to:

write the data stored in the first sub-block into the second block with a first error correction coding, and

write the data stored in the second sub-block into the third block with a second error correction coding having an error correction capability not higher than an error correction capability of the first error correction coding.

16. The memory system according to claim 13 , wherein the controller is further configured to:

write the data stored in the first sub-block into the second block by a first write method so that a threshold voltage distribution of nonvolatile memory cells in the second block has a first center voltage, and

write the data stored in the second sub-block into the third block by a second write method so that a threshold voltage distribution of nonvolatile memory cells in the third block has a second center voltage, wherein

the first center voltage is higher than the second center voltage.

17. The memory system according to claim 13 , wherein the controller is further configured to perform garbage collection and control the movement of data stored in the at least one of the sub-blocks by the garbage collection.

18. The memory system according to claim 13 , wherein the at least one of the sub-blocks includes at least one of

a group of the nonvolatile memory cells connected to a word line,

a group of the nonvolatile memory cells connected to word lines, or

a group of the nonvolatile memory cells storing data specified by a logical address range.