IP Library Granted Patent US 10,485,097
Granted Patent B2
US 10,485,097 · App. 16/214,298 · Granted Nov 19, 2019

Backplane footprint for high speed, high density electrical connectors

Inventors: Marc Robert Charbonneau (Bedford, NH); Jose Ricardo Paniagua (Newmarket, NH)
Assignee: Amphenol Corporation
H05K1/0245H01R12/7082H01R12/716H05K1/0219H05K1/0251H05K1/115H05K3/429H05K1/0225H05K2201/096H05K2201/09727H05K2201/09845
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Quick Facts
Patent No.
US 10,485,097
App. No.
16/214,298
Granted
Nov 19, 2019
Kind
B2
Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.

Claims (12)

1. A printed circuit board comprising:

a plurality of layers including attachment layers and routing layers; and

columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising:

first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers to at least one breakout layer of the routing layers;

at least one antipad surrounding the first and second signal vias; and

first and second conductive shadow vias located between the first and second signal vias of the differential pair on a first line that is perpendicular to a second line through the first and second signal vias and that is midway between the first and second signal vias.

2. The printed circuit board as defined in claim 1 , wherein the first and second shadow vias are smaller in diameter than the first and second signal vias.

3. The printed circuit board as defined in claim 1 , further comprising additional shadow vias located between adjacent via patterns in each of the columns.

4. The printed circuit board as defined in claim 1 , wherein the first and second shadow vias contact opposite sides of the antipad and divide the antipad into first and second sections surrounding the first and second signal vias, respectively.

5. The printed circuit board as defined in claim 1 , wherein each of the first and second shadow vias is equally spaced from the first and second signal vias.

6. The printed circuit board as defined in claim 1 , wherein the at least one antipad comprises a first antipad surrounding the first signal via and a second antipad surrounding the second signal via and wherein first and second signal traces are connected to the first and second signal vias, respectively, in a breakout layer of the routing layers and wherein the first and second antipads in a layer below the breakout layer include ground plane projections toward the first and second signal vias underneath the first and second signal traces.

7. The printed circuit board as defined in claim 6 , wherein each of the first and second signal traces includes a widened portion near the respective first and second signal vias.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2019
From: CHARBONNEAU, MARC ROBERT; PANIAGUA, JOSE RICARDO
To: AMPHENOL CORPORATION
Reel/Frame 047943/0640 →
Continuity (3)
Division 15452096 · Mar 7, 2017
Provisional Application 62305049 · Mar 8, 2016
Related Publication 20190110359A1 · Apr 11, 2019
Cited By (5)
US 1,067,191 US 1,068,685 US 12,207,395 US 12,309,915 US 12,444,863