IP Library Granted Patent US 10,714,455
Granted Patent B2
US 10,714,455 · App. 16/215,449 · Granted Jul 14, 2020

Integrated circuit package assemblies including a chip recess

Inventors: Georg Seidemann (Landshut, DE); Klaus Reingruber (Langquaid, DE)
Assignee: Intel IP Corporation
H01L25/0657H01L23/49833H01L24/20H01L24/96H01L24/97H01L25/105H01L25/50H01L23/367H01L23/49816H01L23/49827H01L23/5384H01L23/5385H01L2224/12105H01L2224/16145H01L2224/16227H01L2224/48145H01L2224/73259H01L2224/73277H01L2225/06506H01L2225/06513H01L2225/06548H01L2225/06555H01L2225/06568H01L2225/06582H01L2225/06589H01L2225/1035H01L2225/1058H01L2225/1094H01L2924/14H01L2924/1432H01L2924/1434H01L2924/1436H01L2924/1438H01L2924/1461H01L2924/15311H01L2924/15321
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Quick Facts
Patent No.
US 10,714,455
App. No.
16/215,449
Granted
Jul 14, 2020
Kind
B2
Abstract

IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.

Claims (37)

1. A method of assembling an integrated circuit (IC) package, the method comprising:

receiving an IC chip having a front side including a plurality of first metal features, and a back side separated from the front side by an initial chip z-thickness;

forming a molding compound around a perimeter of the IC chip, wherein forming the molding compound contacts a sidewall of the IC chip with the molding compound;

recessing the IC chip back side relative to a back side of the molding compound by removing a thickness of a semiconductor substrate with a process that exposes a sidewall of at least some of the molding compound that was in contact with a portion of the sidewall of the IC chip; and

stacking a component having a smaller area than that of the IC chip within a recess over the recessed back side of the IC chip and spaced apart from the sidewall of the molding compound.

2. The method of claim 1 , further comprising:

forming electrical connections between the first metal features and a first package substrate; and

forming electrical connections between the first package substrate and second metal features that are over a front side of the molding compound.

3. The method of claim 1 , wherein stacking the component further comprises placing at least one of a second IC chip, ora MEMs device, or a metal heat spreader within a recess over the IC chip, and framed by the molding compound.

4. The method of claim 1 , further comprising:

forming conductive vias in the molding compound, the vias extending between the back side of the compound and a front side of the compound; and

wherein the stacking the component comprises:

forming electrical connections between a second IC chip and a package substrate; and

forming electrical connections between the package substrate and the conductive vias.

5. The method of claim 1 , wherein stacking the component further comprises placing a metal block within the recess.

6. The method of claim 5 , further comprising stacking another component over the metal block, on a side of the heat spreader opposite the IC chip.

7. The method of claim 6 , wherein stacking another component comprises stacking a second IC chip over the metal block.

8. The method of claim 7 , wherein stacking the second IC chip over the metal block further comprises attaching a package substrate to the back side of the molding compound.

9. The method of claim 1 , further comprising coupling the IC chip to a power supply.

10. A method of assembling an integrated circuit (IC) package, the method comprising:

forming a molding compound around a perimeter of an IC chip, the IC chip having a front side including a plurality of first metal features, and a back side separated from the front side by a chip z-thickness, wherein forming the molding compound around a perimeter of an IC chip contacts a sidewall of the IC chip with the molding compound;

reducing the chip z-thickness by reducing a thickness of a semiconductor substrate with a recessing process that exposes at least some of the molding compound that was in contact with a portion of the sidewall; and

stacking a second IC chip over the IC chip, wherein stacking the second IC chip over the IC chip comprises forming a heat spreader within a recess over the back side of the IC chip, and stacking the second IC chip over the heat spreader, on a side of the heat spreader opposite the IC chip.

11. The method of claim 10 , wherein stacking the second IC chip over the IC chip comprises affixing a package substrate to the back side of the molding compound, the second IC chip attached to the package substrate.

12. The method of claim 11 , further comprising:

forming vias through the molding compound; and

interconnecting the vias to interconnect features of the package substrate.

13. The method of claim 12 , wherein interconnecting the vias to interconnect features of the package substrate comprises reflowing solder features.

14. The method of claim 10 , further comprising forming a channel through a portion of the molding compound, wherein forming the heat spreader further comprises depositing metal with the recess and within the channel.

15. The method of claim 14 , further comprising coupling the heat spreader to a heat sink external of the molding compound.

16. A method of assembling an integrated circuit (IC) package, the method comprising:

forming a molding compound around a perimeter of a IC chip, the IC chip having a front side, and a back side separated from the front side by a chip z-thickness, wherein the forming contacts a sidewall of the IC chip with the molding compound;

reducing the chip z-thickness by removing, from a back side of the IC chip, a thickness of a semiconductor substrate with a recessing process that exposes at least some of the molding compound that was in contact with a portion of the sidewall; and

stacking at least one of: a MEMs device, a second IC chip, or a heat spreader over the IC chip, at least a portion of the MEMs device, a second IC chip, or a heat spreader adjacent to, and spaced apart from, a sidewall of the molding compound exposed by the recessing of the IC chip back side.

17. The method of claim 16 , wherein the stack further comprises stacking the MEMs device or the second IC chip over the IC chip, and wherein the method further comprises:

forming vias through the molding compound; and

interconnecting the vias to the MEMs device or second IC chip.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057061/0588 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057254/0415 →
Cited By (1)
US 12,604,778