System discovery and signaling

1. A communication system, comprising:

a memory configured to store program instructions; and

a processor, upon executing the program instructions, configured to:

generate a Pseudo-Noise (PN) sequence based on a seed value;

generate a constant amplitude zero auto-correlation (CAZAC) sequence based on a root index value;

map a product of the PN sequence and the CAZAC sequence to a plurality of subcarriers such that each one of the plurality of subcarriers has a subcarrier value, wherein:

a subcarrier value of a DC subcarrier of the plurality of subcarriers is zero,

each component value of the PN sequence associated with the product of the PN sequence and the CAZAC sequence of each subcarrier has reflective symmetry about the DC subcarrier, and

the product of the PN sequence and the CAZAC sequence includes a product of a second sequence and the CAZAC sequence, the second sequence being based on the PN sequence and having reflective symmetry about the DC subcarrier; and

translate the subcarrier values of each one of the plurality of subcarriers to a time domain sequence, wherein one or more receiver devices can perform initial synchronization using the time domain sequence.

2. The system of claim 1 , wherein the time domain sequence is one symbol in a plurality of symbols and the processor, upon executing the program instructions, is further configured to:

map a product of the CAZAC sequence and a second PN sequence to the plurality of subcarriers across each symbol of the plurality of symbols, wherein the second PN sequence is a continuously advancing PN sequence across the plurality of symbols.

3. The system of claim 1 , wherein the time domain sequence is one symbol in a plurality of symbols and the processor, upon executing the program instructions, is further configured to invert, by 180 degrees phase inversion, a CAZAC sequence associated with the plurality of subcarriers of a final symbol of the plurality of symbols relative to a symbol preceding the final symbol to indicate termination of the plurality of symbols.

4. The system of claim 1 , wherein the processor, upon executing the program instructions, is further configured to apply a cyclic shift to the time domain sequence to obtain a shifted time domain sequence.

5. The system of claim 4 , wherein the time domain sequence is one symbol in a plurality of symbols and the processor, upon executing the program instructions, is further configured to generate the cyclic shift of the one symbol based on an absolute cyclic shift of a preceding symbol and a relative cyclic shift of the one symbol, the relative cyclic shift being relative to the absolute cyclic shift of the preceding symbol.

6. The system of claim 5 , wherein the plurality of symbols have a fixed sampling rate and a fixed bandwidth.

7. The system of claim 6 , wherein the fixed sampling rate is 6.144 Msamples/second and the fixed bandwidth is 4.5 MHz.

8. The system of claim 1 , wherein to translate the subcarrier values to the time domain sequence, the processor, upon executing the program instructions, is configured to translate the subcarrier values to the time domain sequence using a 2048-point Inverse Fast Fourier Transform (IFFT).

9. A method, comprising:

generating a Pseudo-Noise (PN) sequence based on a seed value;

generating a constant amplitude zero auto-correlation (CAZAC) sequence based on a root index value;

mapping a product of the PN sequence and the CAZAC sequence to a plurality of subcarriers such that each one of the plurality of subcarriers has a subcarrier value, wherein:

a subcarrier value of a DC subcarrier of the plurality of subcarriers is zero,

each component value of the PN sequence associated with the product of the PN sequence and the CAZAC sequence of each subcarrier has symmetry about the DC subcarrier, and

the product of the PN sequence and the CAZAC sequence includes a product of a second sequence and the CAZAC sequence, the second sequence being based on the PN sequence and having reflective symmetry about the DC subcarrier; and

translating the subcarrier values of each one of the plurality of subcarriers to a time domain sequence, wherein one or more receiver devices can perform initial synchronization using the time domain sequence.

10. The method of claim 9 , wherein the time domain sequence is one symbol in a plurality of symbols and the method further comprising:

mapping a product of the CAZAC sequence and a second PN sequence to the plurality of subcarriers across each symbol of the plurality of symbols, wherein the second PN sequence is a continuously advancing PN sequence across the plurality of symbols.

11. The method of claim 9 , wherein the time domain sequence is one symbol in a plurality of symbols and the method further comprising:

inverting, by 180 degrees phase inversion, a CAZAC sequence associated with the plurality of subcarriers of a final symbol of the plurality of symbols relative to a symbol preceding the final symbol to indicate termination of the plurality of symbols.

12. The method of claim 9 , further comprising:

applying a cyclic shift to the time domain sequence to obtain a shifted time domain sequence, wherein the cyclic shift is representative of communication information; and

transmitting the shifted time domain sequence to the one or more receiver devices.

13. The method of claim 12 , wherein the time domain sequence is one symbol in a plurality of symbols and the method further comprising:

generating the cyclic shift of the one symbol based on an absolute cyclic shift of a preceding symbol and a relative cyclic shift of the one symbol, the relative cyclic shift being relative to the absolute cyclic shift of the preceding symbol.

14. The method of claim 13 , wherein the plurality of symbols have a fixed sampling rate of 6.144 Msamples/second and a fixed bandwidth of 4.5 MHz.

15. The method of claim 9 , wherein the translating the subcarrier values to the time domain sequence comprises:

translating the subcarrier values to the time domain sequence using a 2048-point Inverse Fast Fourier Transform (IFFT).

16. A transmitting device, comprising:

a memory storing program instructions; and

a processor, upon executing the program instructions, configured to:

generate a Pseudo-Noise (PN) sequence based on a seed value;

generate a constant amplitude zero auto-correlation (CAZAC) sequence based on a root index value;

map a product of the PN sequence and the CAZAC sequence to a plurality of subcarriers such that each one of the plurality of subcarriers has a subcarrier value, wherein:

a subcarrier value of a DC subcarrier of the plurality of subcarriers is zero,

each component value of the PN sequence associated with the product of the PN sequence and the CAZAC sequence of each subcarrier has reflective symmetry about the DC, and

the product of the PN sequence and the CAZAC sequence includes a product of a second sequence and the CAZAC sequence, the second sequence being based on the PN sequence and having reflective symmetry about the DC subcarrier;

translate the subcarrier values to a time domain sequence; and

transmit the time domain sequence to one or more receiver devices, wherein the one or more receiver devices can perform initial synchronization using the time domain sequence,

wherein the time domain sequence is one symbol in a plurality of symbols and the processor, upon executing the program instructions, is further configured to invert, by 180 degrees phase inversion, a CAZAC sequence associated with the plurality of subcarriers of a final symbol of the plurality of symbols relative to a symbol preceding the final symbol to indicate termination of the plurality of symbols.

17. The transmitting device of claim 16 , wherein the processor, upon executing the program instructions, is further configured to:

generate a cyclic shift of the one symbol based on an absolute cyclic shift of a preceding symbol and a relative cyclic shift of the one symbol, the relative cyclic shift being relative to the absolute cyclic shift of the preceding symbol; and

apply the cyclic shift to the time domain sequence to obtain a shifted time domain sequence.

18. The transmitting device of claim 17 , wherein to apply the cyclic shift, the processor, upon executing the program instructions, is further configured to:

add the relative cyclic shift and the absolute cyclic shift before applying the cyclic shift.

19. The transmitting device of claim 17 , wherein the shifted time domain sequence comprises control signaling configured to permit reception and decoding of a waveform.