Digital logic compatible inputs in compound semiconductor circuits

1. An apparatus comprising a III-V compound semiconductor integrated circuit comprising an input buffer circuit configured to provide a digital control interface between internal circuitry and external circuitry connected to an input pin of the III-V compound semiconductor integrated circuit, said input buffer circuit comprising:

a device comprising a semiconductor junction formed in a III-V compound semiconductor material and configured to generate a reference voltage;

a voltage divider circuit formed in said III-V compound semiconductor material and configured to generate a first predetermined threshold voltage in response to the reference voltage;

a comparator circuit formed in said III-V compound semiconductor material and configured to generate a first intermediate signal in response to a comparison of the first predetermined threshold voltage and a digital input signal received at the input pin of the III-V compound semiconductor integrated circuit, said digital input signal having a first logic state represented by a first predefined voltage level and a second logic state represented by a second predefined voltage level; and

a first output circuit formed in said III-V compound semiconductor material and configured to generate a first output signal in response to the first intermediate signal, wherein the first output signal is configured to control the internal circuitry of the III-V compound semiconductor integrated circuit.

2. The apparatus according to claim 1 , wherein:

the comparator circuit is further configured to generate a second intermediate signal in response to the comparison of the first predetermined threshold voltage and the digital input signal; and

the input buffer circuit further comprises a second output circuit formed in said III-V compound semiconductor material and configured to generate a second output signal in response to the second intermediate signal, wherein the second output signal is configured to control the internal circuitry of the III-V compound semiconductor integrated circuit.

3. The apparatus according to claim 2 , wherein:

the second intermediate signal is a complement of the first intermediate signal.

4. The apparatus according to claim 2 , wherein:

the second output signal is a complement of the first output signal.

5. The apparatus according to claim 1 , wherein said III-V compound semiconductor material comprises at least one of a gallium arsenide alloy, a gallium nitride alloy, an indium phosphide alloy, an indium gallium phosphide alloy, and a silicon carbide alloy.

6. The apparatus according to claim 1 , wherein said semiconductor junction comprises at least one of a diode junction, a transistor junction, and a parasitic junction.

7. The apparatus according to claim 1 , wherein said reference voltage is stable over variations in one or more of process, voltage, and temperature.

8. The apparatus according to claim 1 , wherein said first predetermined threshold voltage is selected to be compliant with one or more digital logic standards.

9. The apparatus according to claim 1 , wherein said first predetermined threshold voltage is selected to be compliant with one or more complementary metal-oxide-semiconductor (CMOS) logic standards.

10. The apparatus according to claim 1 , wherein said device comprising said semiconductor junction generates said reference voltage for at least one of (i) a single-bit input buffer circuit, (ii) a multi-bit input buffer circuit, and (iii) two or more input buffer circuits.

11. The apparatus according to claim 1 , wherein:

said apparatus further comprises a digital control circuit coupled to said III-V compound semiconductor integrated circuit and configured to present said digital input signal to the input pin of said III-V compound semiconductor integrated circuit.

12. The apparatus according to claim 11 , wherein said digital control circuit comprises a complementary metal oxide semiconductor integrated circuit.