Semiconductor light emitting device with light extraction structures
A light emitting device is described. The light emitting device includes a substrate and a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region and has a first surface adjacent the substrate and a second surface opposite the first surface. The first surface of the semiconductor structure multiple cavities formed therein, which extend into at least one of the n-type region and the p-type region. The cavities are spaced apart and lined by a dielectric layer. At least a portion of the second surface is roughened to form multiple features spaced apart at a distance smaller than a distance between each of the cavities formed in the first surface to enhance extraction of light emitted from the light emitting layer. At least one contact is disposed between the first surface of the semiconductor structure and the substrate.
1. A light emitting device comprising:
a semiconductor structure comprising a light emitting layer between an n-type region and a p-type region, a plurality of cavities being formed in a surface of the semiconductor structure and extending at least into the p-type region, each of the plurality of cavities having a hexagon-shaped cross section and a reflective surface; and
a plurality of electrical contacts, a respective one of the plurality of electrical contacts electrically coupled between the p-type region and a respective one of the plurality of cavities.
2. The light emitting device of claim 1 , wherein an area of the hexagonal-shaped cross section is larger than an area of the p-contact.
3. The light emitting device of claim 1 , wherein each of the plurality of cavities is electrically coupled to a respective one of the plurality of electrical contacts.
4. The light emitting device of claim 1 , wherein a subset of the plurality of cavities are electrically coupled to a respective one of the plurality of electrical contacts.
5. The light emitting device of claim 1 , wherein sidewalls of each of the plurality of cavities have sidewall angles between 35° and 55°.
6. The light emitting device of claim 1 , further comprising a plurality of other electrical contacts electrically coupled to the n-type region.
7. The light emitting device of claim 1 , wherein at least one of a size, a shape and a spacing of the plurality of cavities is selected to direct light incident on the plurality of cavities, at a range of angles greater than 70° relative to a normal to the second surface, out of the semiconductor structure via the second surface.
8. The light emitting device of claim 1 , further comprising a substrate adjacent the surface of the semiconductor structure in which the plurality of cavities are formed.
9. The light emitting device of claim 1 , wherein a surface of the n-type region is textured.
10. A method of manufacturing a light emitting device, the method comprising:
forming a p-type layer, a light emitting layer, and an n-type layer on a substrate;
removing the substrate;
etching a plurality of cavities having hexagon-shaped cross-sections into a surface of the semiconductor structure and extending at least into the p-type layer; and
disposing a metal material in each of the plurality of cavities.
11. The method of claim 10 , further comprising forming a respective electrical contact between at least a subset of the plurality of cavities and the p-type layer.
12. The method of claim 11 , wherein the disposing the metal material in each of the plurality of cavities comprising filling at least a subset of the plurality of cavities with a metal material at the same time that the respective electrical contact is formed.
13. The method of claim 11 , wherein the etching the plurality of cavities further comprises etching a plurality of cavities having hexagon-shaped cross sections having an area larger than an area of the p-contact.
14. The method of claim 10 , further comprising etching a plurality of mesas in the surface of the semiconductor structure and extending through the p-type region and the active region and at least partially into the n-type region.
15. The method of claim 14 , further comprising forming an electrical contact in each of the plurality of mesas.
16. The method of claim 10 , wherein the etching the plurality of cavities further comprising etching a plurality of cavities having sidewalls that have sidewall angles between 35° and 55°.
17. The method of claim 10 , further comprising selecting at least one of a size, a shape and a spacing of the plurality of cavities to direct light incident on the plurality of cavities, at a range of angles greater than 70° relative to a normal to the second surface, out of the semiconductor structure via the second surface.
18. The method of claim 10 , wherein the forming the p-type layer, the light emitting layer and the n-type layer comprises growing the p-type layer, the light emitting layer and the n-type layer on a growth substrate.
19. The method of claim 10 , further comprising texturing the n-type layer.
20. The method of claim 10 , further comprising bonding a semiconductor structure formed of the p-type layer, the light emitting layer, and the n-type layer to a substrate.