Multi-layer inter-gate dielectric structure and method of manufacturing thereof

1. A semiconductor device, comprising:

a substrate;

a first gate structure having a first gate conducting layer and a first gate dielectric structure between the first gate conducting layer and the substrate;

a second gate structure having a second gate conducting layer and a second gate dielectric structure between the second gate conducting layer and the substrate; and

an inter-gate dielectric structure disposed between the first gate structure and the second gate structure, wherein the inter-gate dielectric structure includes four or more layers of two or more different dielectric films disposed in an alternating manner, and wherein each of the four or more layers includes a width in an approximate range of 30 Å or less, and less than a predetermined value such that its wet etch rate is significantly less than its bulk etch rate.

2. The semiconductor device of claim 1 , wherein the inter-gate dielectric structure comprises four alternating oxide and nitride films.

3. The semiconductor device of claim 2 , wherein the inter-gate dielectric structure comprises at least one further layer of oxide film.

4. The semiconductor device of claim 2 , wherein the inter-gate dielectric structure comprises at least one further layer of nitride film.

5. The semiconductor device of claim 2 , wherein the inter-gate dielectric structure comprises at least one further alternating pair of oxide and nitride films.

6. The semiconductor device of claim 1 , wherein an exposed surface of the inter-gate dielectric structure that is in a direction perpendicular to the substrate is substantially un-etched.

7. The semiconductor device of claim 1 , wherein the first gate structure comprises a memory gate of a split-gate memory cell.

8. The semiconductor device of claim 1 , wherein the second gate structure comprises a select gate of a split-gate memory cell.

9. The semiconductor device of claim 1 , wherein the two or more different dielectric films have significantly different wet etch rates against a same etchant.

10. A memory device, comprising:

a first gate disposed adjacent to a second gate; and

a first dielectric structure, disposed between the first and second gates, including at least four layers of oxide and nitride films arranged in an alternating layer, wherein each of the at least four or more layers oxide and nitride films includes a width in an approximate range of 30 Å or less and less than a predetermined value such that its wet etch rate is significantly less than its bulk etch rate, and wherein the first dielectric structure includes a top surface that is substantially un-etched.

11. The memory device of claim 10 , further comprising:

a second dielectric structure disposed on a side surface of the first gate that is not adjacent to the second gate, wherein the second dielectric structure includes at least four layers of oxide and nitride films arranged in an alternating layer, wherein each of the at least four or more layers includes a width in an approximate range of 30 Å or less.

12. The memory device of claim 11 , wherein the first gate is a memory gate.

13. The memory device of claim 11 , further comprising:

a dielectric layer disposed over and encapsulating the first and second gates and the first and second dielectric structures.

14. The memory device of claim 10 , wherein the nitride films of the at least four layers of the first dielectric structure includes at least one of silicon nitride, silicon oxynitride (SiON), and silicon carbon nitride (SiCN).

15. The memory device of claim 10 , wherein the oxide films of the at least four layers of the first dielectric structure includes at least one of silicon oxide, aluminum oxide (Al x O y ), hafnium oxide (Hf x O y ), and hafnium aluminum oxide (Hf x Al y O z ).

16. The memory device of claim 10 , wherein the oxide films include silicon oxide and the nitride films include silicon nitride, wherein the oxide films are fabricated by oxidizing portions of the nitride films resulting in interface layers including silicon oxynitride disposed between the oxide and nitride films.

17. The memory device of claim 10 , wherein the first dielectric structure has a width in an approximate range of 100 Å to 200 Å.

18. The memory device of claim 10 , wherein the width of each of the at least four layers of oxide and nitride films is substantially the same.

19. The memory device of claim 10 , wherein at least one of the widths of the at least four layers of oxide and nitride films is different from the rest of the at least four layers of oxide and nitride films.